Design and Analysis of N-Type CNTFET Based 2 X 1 Multiplexer

2012 ◽  
Vol 229-231 ◽  
pp. 1656-1661 ◽  
Author(s):  
Y. Varthamanan ◽  
V. Kannan
Keyword(s):  
Power Dissipation ◽  
Power Analysis ◽  
Operating Voltage ◽  
Resistive Load ◽  
Efficient Design ◽  
Short Channel ◽  
Channel Effect ◽  
Promising Application ◽  
Carbon Nano Tube ◽  
Efficient Power

This paper enumerates the efficient design and analysis of N-type CNTFET based 2X1 Multiplexer. The Multiplexer is designed using Ballistic CNTFET (VHDL-AMS model) with the dcnt of 1nm in resistive load inverter logic. The transient and power analysis are obtained with operating voltage at 0.6V for the multiplexer using system vision tool. There are many issues facing while integrating many number of transistors like short channel effect, power dissipation, scaling of the transistors. To overcome these problems by Consider the carbon nano tube(CNT) have promising application in the field of electronics. The simulation results are presented, and the power consumptions are compared with the conventional MOSFET design. The comparison of results indicated that the CNTFET based design is capable of efficient power savings.

scholarly journals Reliability and Power Analysis of FinFET Based SRAM

2021 ◽  
Author(s):  
Alluri Navaneetha ◽  
K. Bikshalu
Keyword(s):  
Power Dissipation ◽  
Power Analysis ◽  
High Reliability ◽  
Standard Test ◽  
Single Chip ◽  
Short Channel ◽  
Technology Roadmap ◽  
Low Leakage ◽  
Channel Effects ◽  
Low Power Dissipation

Abstract Demand for accommodating more and new functionalities within a single chip such as SOC needs a novel devices and architecture such as FinFET device instead of MOSFET. FinFET is emerged as non-planar, multigate device to overcome short channel effects such as subthreshold swing deterioration, drain induced barrier lowering, threshold voltage roll off which degrade circuit performance. As the need of device technology is mounting in electronic gadgets the important parameters are taken into consideration such as low leakage, high reliability, low power dissipation, and high operating speed. Reliability is one of key considerations in converting a proof of concept into reality. In this work Reliability of FinFET device is studied experimentally according to ITRS (international technology roadmap for semiconductor) roadmap using several standard test protocols such as multiple current stressing, harsher environment conditions, and effect of electromigration. Furthermore, power analysis of FinFET based SRAM is done by using 7nm bsimcmg PTM files in mentor graphics tool. The FinFET based SRAM shown low leakage, power dissipation, delay compared to existing conventional MOSFET based SRAM.

Analysis of an Anomalous Transistor Exhibiting Dual-Vt Characteristics and Its Cause in a 90nm Node CMOS Technology

2012 ◽  
Author(s):  
Yuk L. Tsang ◽  
Xiang D. Wang ◽  
Reyhan Ricklefs ◽  
Jason Goertz
Keyword(s):  
Threshold Voltage ◽  
Electrical Characterization ◽  
Cmos Technology ◽  
Short Channel ◽  
Visual Defect ◽  
Subthreshold Region ◽  
Short Channel Effect ◽  
Channel Effect ◽  
Transistor Model

Abstract In this paper, we report a transistor model that has successfully led to the identification of a non visual defect. This model was based on detailed electrical characterization of a MOS NFET exhibiting a threshold voltage (Vt) of just about 40mv lower than normal. This small Vt delta was based on standard graphical extrapolation method in the usual linear Id-Vg plots. We observed, using a semilog plot, two slopes in the Id-Vg curves with Vt delta magnified significantly in the subthreshold region. The two slopes were attributed to two transistors in parallel with different Vts. We further found that one of the parallel transistors had short channel effect due to a punch-through mechanism. It was proposed and ultimately confirmed the cause was due to a dopant defect using scanning capacitance microscopy (SCM) technique.

Improved Short Channel Effect Control in Bulk FinFETs With Vertical Implantation to Form Self-Aligned Halo and Punch-Through Stop Pocket

2015 ◽  
Vol 36 (7) ◽  
pp. 648-650 ◽  
Author(s):  
Miao Xu ◽  
Huilong Zhu ◽  
Lichuan Zhao ◽  
Huaxiang Yin ◽  
Jian Zhong ◽  
...  
Keyword(s):  
Short Channel ◽  
Short Channel Effect ◽  
Channel Effect

Suppression of short channel effect in organic thin film transistors

2007 ◽  
Vol 91 (11) ◽  
pp. 113508 ◽  
Author(s):  
K. Tukagoshi ◽  
F. Fujimori ◽  
T. Minari ◽  
T. Miyadera ◽  
T. Hamano ◽  
...  
Keyword(s):  
Thin Film ◽  
Thin Film Transistors ◽  
Organic Thin Film Transistors ◽  
Organic Thin Film ◽  
Short Channel ◽  
Short Channel Effect ◽  
Channel Effect

scholarly journals Design and Performance Improvement of CNTFET Based Content Addressable Memory (CAM) Cells

2019 ◽  
Vol 9 (1) ◽  
pp. 1694-1698
Keyword(s):  
Performance Improvement ◽  
Power Analysis ◽  
Electronic Device ◽  
Digital Processing ◽  
Basic Component ◽  
Content Addressable Memory ◽  
Innovative Methods ◽  
Scaling Down ◽  
And Performance ◽  
Carbon Nano Tube

The scaling down of transistors is of paramount importance to make ICs and devices more portable and efficient. As it is the most basic component of every electronic device, there is need of finding better and innovative methods of transistor characterization. CNTFET has shown the promise and is best suited for today’s faster digital processing units and Memory devices. Here Carbon Nano Tube (CNT) is characterized for its electrical property and then designed a XOR based CAM cell using CNTFET. Both delay and power analysis for the designed CAM is done.

scholarly journals Design of low power 8-bit gate-diffusion input (GDI) full adder using variable body bias (VBB) technique in 90nm technology

2019 ◽  
Vol 14 (2) ◽  
pp. 912
Author(s):  
Woo Wei Kai ◽  
Nabihah Ahmad ◽  
Mohamad Hairol Jabbar
Keyword(s):  
Low Power ◽  
Average Power ◽  
Full Adder ◽  
Oxide Thickness ◽  
Low Complexity ◽  
Operating Voltage ◽  
Short Channel ◽  
Static Power ◽  
Subthreshold Leakage ◽  
Power Delay Product

In digital system, the full adders are fundamental circuits that are used for arithmetic operations. Adder operation can be used to implement and perform calculation of the multipliers, subtraction, comparators, and address operation in an Arithmetic Logic Unit (ALU). The subthreshold leakage current increasing as proportional with the scaling down of oxide thickness and transistor in short channel sizes. In this paper, a Gate-diffusion Input (GDI) circuit design technique allow minimization the number of transistor while maintaining low complexity of logic design and low power realization of Variable Body Biasing (VBB) technique to reduce the static power consumption. The Silterra 90nm process design kit (PDK) was used to design 8-bit full adder with VBB technique in full custom methodology by using Synopsys Electronic Design Automation (EDA) tools. The simulation of 8-bit full adder was compared within a conventional bias technique and VBB technique with operating voltage of  supply. The result showed the reduction of VBB technique in term of peak power,  and average power,   compare with conventional bias technique. Moreover, the Power Delay Product (PDP) showed 1.29pJ in VBB technique compare with conventional bias mode 1.67pJ. The area size of 8-Bit full adder was 10μm×23μm.

Effects of ultra-thin Si-fin body widths upon SOI PMOS FinFETs

2018 ◽  
Vol 32 (15) ◽  
pp. 1850157 ◽  
Author(s):  
Yue-Gie Liaw ◽  
Chii-Wen Chen ◽  
Wen-Shiang Liao ◽  
Mu-Chun Wang ◽  
Xuecheng Zou
Keyword(s):  
Gate Oxide ◽  
Silicon On Insulator ◽  
Double Gate ◽  
Current Crowding ◽  
Crowding Effect ◽  
Short Channel ◽  
Channel Mobility ◽  
Channel Effect ◽  
193 Nm ◽  
Dry Etch

Nano-node tri-gate FinFET devices have been developed after integrating a 14 Å nitrided gate oxide upon the silicon-on-insulator (SOI) wafers established on an advanced CMOS logic platform. These vertical double gate (FinFET) devices with ultra-thin silicon fin (Si-fin) widths ranging from 27 nm to 17 nm and gate length down to 30 nm have been successfully developed with a 193 nm scanner lithography tool. Combining the cobalt fully silicidation and the CESL strain technology beneficial for PMOS FinFETs was incorporated into this work. Detailed analyses of [Formula: see text]–[Formula: see text] characteristics, threshold voltage [Formula: see text], and drain-induced barrier lowering (DIBL) illustrate that the thinnest 17 nm Si-fin width FinFET exhibits the best gate controllability due to its better suppression of short channel effect (SCE). However, higher source/drain resistance [Formula: see text], channel mobility degradation due to dry etch steps, or “current crowding effect” will slightly limit its transconductance [Formula: see text] and drive current.

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