scholarly journals A Novel Approach to Investigate Analog and Digital Circuit Applications of Silicon Junctionless-Double-Gate (JL-DG) MOSFETs

2021 ◽  
Author(s):  
Abhinav Gupta ◽  
Manish Kumar Rai ◽  
Amit Kumar Pandey ◽  
Digvijay Pandey ◽  
Sanjeev Rai
Keyword(s):  
Output Voltage ◽  
Logic Gate ◽  
Digital Circuit ◽  
Double Gate ◽  
Switching Voltage ◽  
Cmos Inverter ◽  
Small Current ◽  
Noise Margin ◽  
Novel Approach ◽  
Dg Mosfet

Abstract The double gate junctionless transistor (DG-JLT) has become the most promising device in sub nano-meter regime. DGJLT based circuits have improved performance and simpler fabrication than their inversion mode counterparts. This paper demonstrates the design of different analog and digital circuits using DGJLT. Amplifiers and inverters are the basic building block of electronic ICs. A MOS amplifier converts the variation of the gate to source voltage to a small current under transconductance and hence, the output voltage. A single-stage amplifier and differential amplifier have been designed with junctionless-double-gate (JL-DG) MOSFET. Trans-conductance, output voltage, and gain have been investigated using ATLAS 2D device simulator. The inverter is the primary logic gate that can be used to verify the device's response in digital applications. Further, CMOS inverter have been designed using JL-DG MOSFET, and its performance parameters such as switching voltage, noise margin, and logic delay have been analyzed. A switching voltage of 0.43 V, noise margin of 0.265 V, and a delay of 19.18 psec have been obtained for the basic cell. CMOS inverter using JL-DG MOSFET at 20 nm technology node have prompted better performance results. Thus, The JL-DG MOSFET has a bright future in low-power analog and digital applications.

scholarly journals Realization with Fabrication of Double-Gate MOSFET Based Buck Regulator

2021 ◽  
pp. 66-75
Author(s):  
Simone Leeuw ◽  
◽  
Viranjay M. Srivastava
Keyword(s):  
Output Voltage ◽  
High Efficiency ◽  
Research Work ◽  
Drain Current ◽  
Input Voltage ◽  
Switching Frequency ◽  
Maximum Output ◽  
Double Gate ◽  
Dg Mosfet ◽  
Double Gate Mosfet

The traditional buck regulator provides the steady output voltage with high efficiency and low power dissipation. Various parameters of this regulator can be improved by the placement of Double-Gate (DG) MOSFET. The double-gate MOSFET provides twice the drain current flow, which improves the various parameters of buck regulator structure and inevitably increases the device performance and efficiency. In this research work, these parameters have been analyzed with implemented DG MOSFET buck regulator and realized the total losses 42.676 mW and efficiency 74.208%. This research work has designed a DG MOSFET based buck regulator with the specification of input voltage 12 V, output voltage 3.3 V, maximum output current 40 mA, switching frequency 100 kHz, ripple current of 10%, and ripple voltage of 1%.

scholarly journals A Novel Approach to Investigate Analog and Digital Circuit Applications of Silicon Junctionless-Double-Gate (JL-DG) MOSFETs

Silicon ◽  
2021 ◽  
Author(s):  
Abhinav Gupta ◽  
Manish Kumar Rai ◽  
Amit Kumar Pandey ◽  
Digvijay Pandey ◽  
Sanjeev Rai
Keyword(s):  
Digital Circuit ◽  
Double Gate ◽  
Novel Approach

The Three-Level Sine-Wave Inverter with Power Factor Correction (PFC)

2015 ◽  
Vol 781 ◽  
pp. 402-405
Author(s):  
Napat Krachangchaeng ◽  
Sakorn Po-Ngam
Keyword(s):  
Power Factor ◽  
Output Voltage ◽  
Power Factor Correction ◽  
Sine Wave ◽  
Input Power ◽  
Small Current ◽  
Uninterruptible Power Supply ◽  
Current Harmonics ◽  
Electric Device ◽  
Uninterruptible Power

Nowadays, the uninterruptible power supply (UPS) is important in reliability for electric device. The UPS need high quality electricity. Therefore, the simulation of the three-level sine-wave inverter with power factor correction (PFC) is proposed in this paper. Moreover, the circuit’s guidelines of the active PFC controller in the active PFC and the sinusoidal output voltage are also presented. Validity of the proposed the three-level sine-wave inverter with the active PFC is confirmed by simulation. The simulation results show the very small current harmonics, the input power factor most nearly unity and constant output voltage when the suddenly step-load changed.

Modeling of electrical behavior of undoped symmetric Double-Gate (DG) MOSFET using carrier-based approach

2019 ◽  
Vol 38 (2) ◽  
pp. 815-828
Author(s):  
Ajay Kumar Singh
Keyword(s):  
Poisson’S Equation ◽  
Analytical Models ◽  
Double Gate ◽  
Poisson's Equation ◽  
Short Channel ◽  
Content Type ◽  
Dg Mosfet ◽  
Channel Potential ◽  
Work Functions ◽  
Long Channel

Purpose This study aims to develop a compact analytical models for undoped symmetric double-gate MOSFET based on carrier approach. Double-Gate (DG) MOSFET is a newly emerging device that can potentially further scale down CMOS technology owing to its excellent control of short channel effects, ideal subthreshold slope and free dopant-associated fluctuation effects. DG MOSFET is of two types: the symmetric DG MOSFET with two gates of identical work functions and asymmetric DG MOSFET with two gates of different work functions. To fully exploit the benefits of DG MOSFETs, the body of DG MOSFETs is usually undoped because the undoped body greatly reduces source and drain junction capacitances, which enhances the switching speed. Highly accurate and compact models, which are at the same time computationally efficient, are required for proper modeling of DG MOSFETs. Design/methodology/approach This paper presents a carrier-based approach to develop a compact analytical model for the channel potential, threshold voltage and drain current of a long channel undoped symmetric DG MOSFETs. The formulation starts from a solution of the 2-D Poisson’s equation in which mobile charge term has been included. The 2-D Poisson’s equation in rectangular coordinate system has been solved by splitting the total potential into long-channel (1-D Poisson’s equation) and short-channel components (remnant 2-D differential equation) in accordance to the device physics. The analytical model of the channel potential has been derived using Boltzmann’s statistics and carrier-based approach. Findings It is shown that the metal gate suppresses the center potential more than the poly gate. The threshold voltage increases with increasing metal work function. The results of the proposed models have been validated against the Technology Computer Aided Design simulation results with close agreement. Originality/value Compact Analytical models for undoped symmetric double gate MOSFETs.

scholarly journals VLSI Implementation of Hybrid Wave-Pipelined 2D DWT Using Lifting Scheme

VLSI Design ◽  
2008 ◽  
Vol 2008 ◽  
pp. 1-8
Author(s):  
G. Seetharaman ◽  
B. Venkataramani ◽  
G. Lakshminarayanan
Keyword(s):  
Digital Circuit ◽  
San Jose ◽  
Hybrid Wave ◽  
Hybrid Scheme ◽  
Clock Skew ◽  
Clock Period ◽  
Novel Approach ◽  
Clock Routing ◽  
Wave Pipelining ◽  
On Chip

A novel approach is proposed in this paper for the implementation of 2D DWT using hybrid wave-pipelining (WP). A digital circuit may be operated at a higher frequency by using either pipelining or WP. Pipelining requires additional registers and it results in more area, power dissipation and clock routing complexity. Wave-pipelining does not have any of these disadvantages but requires complex trial and error procedure for tuning the clock period and clock skew between input and output registers. In this paper, a hybrid scheme is proposed to get the benefits of both pipelining and WP techniques. In this paper, two automation schemes are proposed for the implementation of 2D DWT using hybrid WP on both Xilinx, San Jose, CA, USA and Altera FPGAs. In the first scheme, Built-in self-test (BIST) approach is used to choose the clock skew and clock period for I/O registers between the wave-pipelined blocks. In the second approach, an on-chip soft-core processor is used to choose the clock skew and clock period. The results for the hybrid WP are compared with nonpipelined and pipelined approaches. From the implementation results, the hybrid WP scheme requires the same area but faster than the nonpipelined scheme by a factor of 1.25–1.39. The pipelined scheme is faster than the hybrid scheme by a factor of 1.15–1.39 at the cost of an increase in the number of registers by a factor of 1.78–2.73, increase in the number of LEs by a factor of 1.11–1.32 and it increases the clock routing complexity.

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