РАЗРАБОТКА И ИССЛЕДОВАНИЕ СВЕТОДИОДНОГО ДРАЙВЕРА

2020 ◽  
Vol 96 (3s) ◽  
pp. 631-634
Author(s):  
О.Л. Климов ◽  
С.М. Игнатьев ◽  
И.В. Ермаков
Keyword(s):  
Research And Development ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Output Current ◽  
Led Driver ◽  
Voltage Range ◽  
Temperature Range ◽  
Current Consumption ◽  
Current Error

Представлены результаты разработки и исследования светодиодного драйвера в КМОП-технологии уровня 0,6 мкм. Погрешность выходного тока драйвера с учетом технологического разброса в диапазоне напряжений питания от 4 до 20 В и диапазоне температур от -60 до +125 °С составила менее ±5 % от номинального значения 3,55 мА. Ток потребления драйвера - менее 100 мкА, а занимаемая площадь - 0,3 х 0,3 мм2. The paper presents the research and development of the LED driver in 0.6 μm CMOS technology. When the supply voltage range is from 4 to 20 V and temperature range is from -60 to +125 °C the output current error of the LED driver taking into account the process corners is less than ±5 % of the nominal value 3.55 mA. The LED driver current consumption is less than 100 uA and the area is less than 0.3 х 0.3 mm2.

scholarly journals Low-Power CMOS Integrated Hall Switch Sensor

2017 ◽  
Vol 2017 ◽  
pp. 1-9 ◽  
Author(s):  
Rongshan Wei ◽  
Shizhong Guo ◽  
Shanzhi Yang
Keyword(s):  
Supply Voltage ◽  
Reducing Power ◽  
Cmos Technology ◽  
Sleep Mode ◽  
Test Results ◽  
Offset Voltage ◽  
Current Consumption ◽  
Low Power Cmos ◽  
Switch Circuit ◽  
Hall Element

This paper presents an integrated Hall switch sensor based on SMIC 0.18 µm CMOS technology. The system includes a front-end Hall element and a back-end signal processing circuit. By optimizing the structure of the Hall element and using the orthogonal coupling and spinning current technology, the offset voltage can be suppressed effectively. The simulation results showed that the Hall switch can eliminate offset voltage greater than 1 mV at 3.3 V supply voltage. Two modes of the Hall switch circuit, the awake mode and the sleep mode, were realized by using clock logic signals without compromising the performance of the Hall switch, thereby reducing power consumption. The test results showed that the operate point and the release point of the switch were within the range of 3–7 mT at 3.3 V supply voltage. Meanwhile, the current consumption is 7.89 µA.

130 nm CMOS Bulk-Driven Variable Gain Amplifier for Low-Voltage Applications

2017 ◽  
Vol 26 (08) ◽  
pp. 1740003 ◽  
Author(s):  
Daniel Arbet ◽  
Viera Stopjaková ◽  
Martin Kováč ◽  
Lukáš Nagy ◽  
Matej Rakús ◽  
...  
Keyword(s):  
Low Voltage ◽  
Supply Voltage ◽  
Input Voltage ◽  
Cmos Technology ◽  
Variable Gain Amplifier ◽  
Voltage Range ◽  
Variable Gain ◽  
Wide Scale ◽  
Simulation Results ◽  
Low Supply Voltage

In this paper, a variable gain amplifier (VGA) designed in 130 nm CMOS technology is presented. The proposed amplifier is based on the bulk-driven (BD) design approach, which brings a possibility to operate with low supply voltage. Since the supply voltage of only 0.6 V is used for the amplifier to operate, there is no risk of latch-up event that usually represents the main drawback of the BD circuit systems. BD transistors are employed in the input differential stage, which makes it possible to operate in rail-to-rail input voltage range. Achieved simulation results indicate that gain of the proposed VGA can be varied in a wide scale, which together with the low supply voltage feature make the proposed amplifier useful for low-voltage and low-power applications. An additional circuit responsible for maintaining the linear-in-decibel gain dependency of the VGA is also addressed. The proposed circuit block avails arbitrary shaping of the curve characterizing the gain versus the controlling voltage dependency.

A Robust SRAM Design for Ultra Dynamic Voltage Scalable VLSI System

2012 ◽  
Vol 182-183 ◽  
pp. 450-455
Author(s):  
Jun Yang ◽  
Na Bai ◽  
Wei Qi Wu ◽  
Wei Wei Shan ◽  
Zhi Kuang Cai
Keyword(s):  
Energy Supply ◽  
Supply Voltage ◽  
Schmitt Trigger ◽  
Cmos Technology ◽  
Dynamic Voltage Scaling ◽  
Voltage Range ◽  
Optimum Energy ◽  
Sram Design ◽  
Vlsi System ◽  
Dynamic Voltage

In this paper, a SRAM array targeting IBM 130nm CMOS technology is proposed for ultra dynamic voltage scaling (UDVS) application with better immunity against process variation. A type of modified Schmitt Trigger inverter is adopted in the SRAM design, which guarantee stable operations in both superthreshold and subthreshold supply voltage regions. Testing results demonstrate that the proposed SRAM array functions well in the supply voltage range of 150 mV to 1200 mV. The optimum-energy supply voltage point is about 400 mV for proposed UDVS SRAM array. And the energy at 400 mV decreases by 62.5% compared to that at 1200 mV.

scholarly journals CMOS Low-Dropout Voltage Regulator Design Trends: An Overview

Electronics ◽  
2022 ◽  
Vol 11 (2) ◽  
pp. 193
Author(s):  
Mohammad Arif Sobhan Bhuiyan ◽  
Md. Rownak Hossain ◽  
Khairun Nisa’ Minhad ◽  
Fahmida Haque ◽  
Mohammad Shahriar Khan Hemel ◽  
...  
Keyword(s):  
High Performance ◽  
Supply Voltage ◽  
Process Variations ◽  
Cmos Technology ◽  
Optimization Techniques ◽  
Oxide Semiconductor ◽  
Voltage Regulator ◽  
Stable Operation ◽  
Short Channel ◽  
Voltage Range

Systems-on-Chip’s (SoC) design complexity demands a high-performance linear regulator architecture to maintain a stable operation for the efficient power management of today’s devices. Over the decades, the low-dropout (LDO) voltage regulator design has gained attention due to its design scalability with better performance in various application domains. Industry professionals as well as academia have put forward their innovations such as event-driven explicit time-coding, exponential-ratio array, switched RC bandgap reference circuit, etc., to make a trade-off between several performance parameters such as die area, ripple rejection, supply voltage range, and current efficiency. However, current LDO architectures in micro and nanometer complementary metal–oxide–semiconductor (CMOS) technology face some challenges, such as short channel effects, gate leakage, fabrication difficulty, and sensitivity to process variations at nanoscale. This review presents the LDO architectures, optimization techniques, and performance comparisons in different LDO design domains such as digital, analog, and hybrid. In this review, various state-of-the-art circuit topologies, deployed for the betterment of LDO performance and focusing on the specific parameter up-gradation to the overall improvement of the functionality, are framed, which will serve as a comparative study and reference for researchers.

Nano Power Current Reference Circuit consisting of Sub-threshold CMOS Circuits

2017 ◽  
Vol 2 (1) ◽  
pp. 1-4
Author(s):  
Dinesh Kushwaha ◽  
D. K. Mishra
Keyword(s):  
Large Scale ◽  
Low Voltage ◽  
Supply Voltage ◽  
Circuit Simulation ◽  
Current Source ◽  
Cmos Technology ◽  
Threshold Region ◽  
Voltage Range ◽  
Current Reference ◽  
Reference Circuit

This paper proposes a low voltage CMOS Nano power current reference circuit and presents its performance with circuit simulation in 180- nm UMC CMOS technology. The proposed circuit consists of start-up, Bias-voltage, current-source sub-circuits with most of the MOSFETs operating in sub-threshold region. Simulation results shows that the circuit generates a stable reference current of 4-nA in supply voltage range 1 V- 1.8 V with line sensitivity of 0.203%/V.The temperature coefficient of the current was 7592ppm/°C at 1.8 V in the range of 0°C-100°C. The power dissipation was 380 NW at 1.8 V Supply. The proposed circuit would be suitable for use in sub-threshold –operated power-aware large-scale integration

scholarly journals A New Rail-to-Rail Second Generation Voltage Conveyor

Electronics ◽  
2019 ◽  
Vol 8 (11) ◽  
pp. 1292 ◽  
Author(s):  
Barile ◽  
Stornelli ◽  
Ferri ◽  
Safari ◽  
D’Amico
Keyword(s):  
Second Generation ◽  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Total Power ◽  
Voltage Range ◽  
Class Ab ◽  
Rail To Rail ◽  
Total Power Consumption ◽  
Voltage Swing

In this paper, a novel low voltage low power CMOS second generation voltage conveyor (VCII) with an improved voltage range at both the X and Z terminals is presented. The proposed VCII is formed by a current buffer based on a class AB regulated common-gate stage and a modified rail-to-rail voltage buffer. Spice simulation results using LFoundry 0.15 μm low-Vth CMOS technology with a ±0.9 V supply voltage are provided to demonstrate the validity of the designed circuit. Thanks to the class AB behavior, from a bias current of 10 µA, the proposed VCII is capable of driving 0.5 mA on the X terminal, with a total power consumption of 120 µW. The allowed voltage swing on the Z terminal is at least equal to ±0.83 V, while on the X terminals it is ±0.72 V. Both DC and AC voltage and current gains are provided, and time domain simulations, where the voltage conveyor is used as a transimpedance amplifier (TIA), are also presented. A final table that summarizes the main features of the circuit, comparing them with the literature, is also given.

scholarly journals AC–DC Flyback Dimmable LED Driver with Low-Frequency Current Ripple Reduced and Power Dissipation in BJT Linearly Proportional to LED Current

Energies ◽  
2020 ◽  
Vol 13 (16) ◽  
pp. 4270
Author(s):  
Yeu-Torng Yau ◽  
Kuo-Ing Hwu ◽  
Kun-Jie Liu
Keyword(s):  
Power Dissipation ◽  
Light Emitting Diode ◽  
Low Frequency ◽  
Output Current ◽  
Led Driver ◽  
Voltage Range ◽  
Flyback Converter ◽  
Linear Current ◽  
Current Ripple ◽  
Frequency Current

In this paper, a dimmable light-emitting diode (LED) driver, along with the low-frequency current ripple decreased and the bipolar junction transistor (BJT) power dissipation reduced, is developed. This driver is designed based on a single-stage flyback converter. On the one hand, the low-frequency output current ripple reduction is based on the physical behavior of the linear current regulator. On the other hand, when the voltage across the LED string is decreased/increased due to dimming or temperature, the output voltage of the flyback converter will be automatically regulated down/up, thereby making the power dissipation in the BJT linearly proportional to the LED current. By doing so, not only the power loss in the linear current regulator will be decreased as the LED current is decreased or the LED temperature rises, but also the output current ripple can be reduced. Furthermore, the corresponding power factor (PF) is almost not changed, and the total harmonic distortion (THD) is improved slightly. In addition, the LED dimming is based on voltage division. Eventually, a 30 W LED driver, with an input voltage range from 85 to 295 Vrms and with 24 LEDs in series used as a load, is developed, and accordingly, the feasibility of the proposed LED driver is validated by experimental results.

Integrated Asymmetrical Half-Bridge Zeta (AHBZ) Converter for DC/DC Stage of LED Driver With Wide Output Voltage Range and Low Output Current

2015 ◽  
Vol 62 (12) ◽  
pp. 7489-7498 ◽  
Author(s):  
Jae-Il Baek ◽  
Jae-Kuk Kim ◽  
Jae-Bum Lee ◽  
Han-Shin Youn ◽  
Gun-Woo Moon
Keyword(s):  
Output Voltage ◽  
Output Current ◽  
Led Driver ◽  
Voltage Range

scholarly journals Body-Effect-Free OLED-on-Silicon Pixel Circuit Based on Capacitive Division to Extend Data Voltage Range

Electronics ◽  
2021 ◽  
Vol 10 (19) ◽  
pp. 2351
Author(s):  
Jina Bae ◽  
Hyoungsik Nam
Keyword(s):  
Threshold Voltage ◽  
Supply Voltage ◽  
The Body ◽  
Body Effect ◽  
Voltage Range ◽  
Error Range ◽  
Large Current ◽  
Voltage Variation ◽  
Current Error ◽  
Node Voltage

This paper proposes an OLED pixel compensation circuit that copes with threshold voltage variation, narrow data voltage range, and body effect on a backplane of silicon-based transistors. It consists of six PMOS transistors and two capacitors. The data voltage range is extended by the capacitor division with two capacitors, and the connection of both source and gate nodes to the supply voltage makes the driving transistor free from the body effect. In addition, the reference voltage is used to initialize the gate node voltage of the driving transistor as well as to adjust the data voltage region. By the SPICE simulation, it is verified that the current error over the threshold voltage variations of ±10 mV is reduced to be −1.200% to 0.964% at the maximum current range of around 8 nA, and the data voltage range is extended to 3.4 V, compared to the large current error range from −21.46% to 27.36% and the data voltage range of 0.41 V in the basic 2T1C circuit. In addition, the body-effect-free circuit outperforms the latest 4T1C circuit of the current error range from −3.279% to 3.388%.

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