scholarly journals Power Factor Corrector Based on Parallel Quasi- Resonant Pulse Converter with Fast Current Loop

2013 ◽  
Vol 3 (1) ◽  
pp. 5-11 ◽  
Author(s):  
Yuriy Denisov ◽  
Serhii Stepenko

Abstract The problems, devoted to power quality and particularly power factor correction, are of great importance nowadays. The key requirements, which should be satisfied according to the energy efficiency paradigm, are not limited only by high quality of the output voltage (low total harmonic distortion), but also assume minimal power losses (high efficiency) in the power factor corrector (PFC). It could be satisfied by the use of quasi-resonant pulse converter (QRPC) due to its high efficiency at high switching frequency instead of the classical pulse-width modulated (PWM) boost converter. A dynamic model of QRPC with zero current switching (ZCS) is proposed. This model takes into account the main features of QRPC-ZCS as a link of a PFC closed-loop system (discreteness, sharp changes of parameters over switching period, input voltage impact on the gain). The synthesized model is also valid for conventional parallel pulse converter over an active interval of commutation. The regulator for current loop of PFC was synthesized based on digital filter using proposed model by the criterion of fast acting.

2015 ◽  
Vol 787 ◽  
pp. 833-837
Author(s):  
Tamizhselvan Annamalai ◽  
V. Rajini

In Green Energy technologies like wind energy conversion systems and Domestic applications like SMPS and UPS systems, the input voltage amplitude and input frequency are time varying in nature. Fast-Escalating and extremely challenging high efficiency requirements for AC-DC power supplies for notebooks, desktop computers are to minimize the power losses (Conduction losses). In the conventional rectifiers power losses are more and power factor is poor resulting in loss of efficiency. Normally, the bridgeless topologies, also referred to as dual boost power factor correction (PFC) rectifiers, may reduce the conduction losses by reducing the number of semi-conductor components in the line current path. Power supply units have to make the load compatible with the source. The presence of non-linear load results in poor power factor operation and produces harmonic components in the line. So PFC techniques are necessary to meet harmonic regulations and standards such as IEC 61000-3-2 and IEEE 519. A modified bridgeless topology may be used for such applications. A novel switching controller is developed that regulates the input resistance to a desired value. Hence input power factor is unity and also the total harmonic distortion is controlled to a tolerable limit. In the proposed model, the modified bridgeless boost converter is activated in to a pure resistance mode. Finally the performance of the modified bridgeless boost converter is compared with the existing basic bridgeless boost converter.


2014 ◽  
Vol 2014 ◽  
pp. 1-8
Author(s):  
Cao Taiqiang ◽  
Chen Zhangyong ◽  
Wang Jun ◽  
Sun Zhang ◽  
Luo Qian ◽  
...  

In order to implement a high-efficiency bridgeless power factor correction converter, a new topology and operation principles of continuous conduction mode (CCM) and DC steady-state character of the converter are analyzed, which show that the converter not only has bipolar-gain characteristic but also has the same characteristic as the traditional Boost converter, while the voltage transfer ratio is not related with the resonant branch parameters and switching frequency. Based on the above topology, a novel bridgeless Bipolar-Gain Pseudo-Boost PFC converter is proposed. With this converter, the diode rectifier bridge of traditional AC-DC converter is eliminated, and zero-current switching of fast recovery diode is achieved. Thus, the efficiency is improved. Next, we also propose the one-cycle control policy of this converter. Finally, experiments are provided to verify the accuracy and feasibility of the proposed converter.


2021 ◽  
Vol 2 (2) ◽  
pp. 29-35
Author(s):  
Dmitry A. Sorokin ◽  
◽  
Sergey I. Volskiy ◽  
Jaroslav Dragoun ◽  
◽  
...  

The paper suggests a control system of a three-phase power factor corrector. The study of the control system operation is carried out and the expressions for calculating the permissible values of error amplifier factors are obtained. The influence of the error amplifier parameters on phase current quality is investigated. The dependence of total harmonic distortion input current on a combination of error amplifier parameters is obtained at a given value of power factor. The conditions under which the total harmonic distortion input current has the minimum value are found out. This article is of interest to power electronics engineers, who are aimed at developing a three-phase power factor corrector.


2012 ◽  
Vol 433-440 ◽  
pp. 5549-5555
Author(s):  
Yun Tao Yue ◽  
Yan Lin

A novel scheme of low power communication power supply with high power factor and soft-switching is presented, a power factor corrector and dc/dc converter of passive lossless soft-switching is based on a ML4803 IC control. DC/DC converter introduces a novel two-transistor forward soft-switching technique, which realizes zero-voltage turn-on and turn-off, with no additional switches. a communication power supply module is developed in this paper. It has the characteristics of rapid dynamic response, high power factor, high efficiency and small bulk ect.


Author(s):  
Nur Arifah Ramli ◽  
Auzani Jidin ◽  
Zulhani Rasin ◽  
Tole Sutikno

Alternating current (AC) electrical drives mainly require smaller current (or torque) ripples and lower total harmonic distortion (THD) of voltage for excellent drive performances. Normally, in practice, to achieve these requirements, the inverter needs to be operated at high switching frequency. By operating at high switching frequency, the size of filter can be reduced. However, the inverter which oftenly employs insulated gate bipolar transistor (IGBT) for high power applications cannot be operated at high switching frequency. This is because, the IGBT switching frequency cannot be operated above 50 kHz due to its thermal restrictions. This paper proposes an alternate switching strategy to enable the use of IGBT for operating the inverter at high switching frequency to improve THD performances. In this strategy, each IGBT in a group of switches in the modified inverter circuit will operate the switching frequency at one-fourth of the inverter switching frequency. The alternate switching is implemented using simple analog and digital integrated circuits.


Electronics ◽  
2018 ◽  
Vol 7 (12) ◽  
pp. 363 ◽  
Author(s):  
Alfredo Medina-Garcia ◽  
Manfred Schlenk ◽  
Diego Morales ◽  
Noel Rodriguez

In this article, an innovative power adaptor based on the asymmetrical pulse width modulation (PWM) flyback topology will be presented. Its benefits compared to other state-of-the-art topologies, such as the active clamp flyback, are analyzed in detail. It will also describe the control methods to achieve high efficiency and power density using zero-voltage switching (ZVS) and zero-current switching (ZCS) techniques over the full range of the input voltage and the output load, providing comprehensive guidelines for the practical design. Finally, we demonstrate the convenience of the proposed design methods with a 65 W adaptor prototype achieving a peak efficiency of close to 95% and a minimum efficiency of 93.4% at full load over the range of the input voltage, as well as a world-class power density of 22 W/inch3 cased.


2018 ◽  
Vol 7 (4.30) ◽  
pp. 240 ◽  
Author(s):  
M. K. R. Noor ◽  
A. Ponniran ◽  
M. A. Z. A. Rashid ◽  
A. A. Bakar ◽  
J. N. Jumadril ◽  
...  

This paper discusses the current total harmonic distortion (THDi) and voltage ripple minimization of SEPIC converter based on parameters design optimization. This conventional PFC SEPIC converter is designed to operate in discontinuous conduction mode in order to achieve almost unity power factor. The passive components, i.e., inductor and capacitor are designed based on switching frequency and resonant frequency. Meanwhile, the ranges of duty cycle for buck and boost operations are between 0<D<0.5 and 0.5<D<1, respectively, for the output voltage variation of the converter. The principle of the parameters design optimization is based on the balancing energy compensation between the input capacitor and output inductor. The experimental results show that, the current THD is reduced to 2.66% from 70.9% after optimization process is conducted. Furthermore, it is confirmed that the output voltage ripple frequency is always double from the input line frequency, fL = 2foutand the output voltage ripple is always lower than the maximum input voltage ripple. Therefore, the designed parameters of the experimental converter is confirmed with approximately 65 W of the converter output power.


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