scholarly journals A Novel Built-in Self Calibration Technique to Minimize Capacitor Mismatch for 12-bit 32MS/s SAR ADC

2015 ◽  
Vol 10 (3) ◽  
pp. 187-200
Author(s):  
Inseok Jung ◽  
Kyung Ki Kim ◽  
Yong-Bin Kim
Keyword(s):  
Sampling Rate ◽  
Cmos Technology ◽  
Sar Adc ◽  
Digital To Analog Converter ◽  
Analog To Digital ◽  
Self Calibration ◽  
Conventional Procedure ◽  
Offset Voltage ◽  
Capacitor Mismatch ◽  
Voltage Amplifier

This paper proposes a novel Built-in Self Calibration (BISC) technique for a 12-bit 32MS/s successive approximation register (SAR) analog-to-digital converter (ADC) using a single input to reduce the capacitor mismatch of the digital-to-analog converter (DAC) and to compensate the comparator input offset voltage. The proposed self-calibration scheme optimize the mismatch of the DAC by changing additional auxiliary capacitor array during calibration mode. In addition, in order to minimize the offset voltage of the comparator in the SAR ADC, a simplified voltage amplifier is proposed. The controller for the proposed algorithm operates as foreground operation to achieve low power consumption during operation. Compared to the converters that use the conventional procedure, INL and DNL are reduced by about 47% and 52%, respectively. The prototype was designed using 130nm single poly 6 metal standard CMOS technology. The ADC achieves a SNDR of 65.6 dB and consumes 4.62 mW. The ADC core occupies an active area of only 240μmÍ 298 μm using 1.2V supply and the sampling rate of 50 MS/s.

scholarly journals A 14-bit High Speed 125MS/s Low Power SAR ADC using Dual Split Capacitor DAC Architecture in 90nm CMOS Technology

2021 ◽  
Vol 15 ◽  
pp. 556-568
Author(s):  
Chaya Shetty ◽  
M. Nagabushanam ◽  
Venkatesh Nuthan Prasad
Keyword(s):  
High Speed ◽  
Signal To Noise Ratio ◽  
Sampling Rate ◽  
Cmos Technology ◽  
Sar Adc ◽  
Cmos Process ◽  
Digital To Analog Converter ◽  
Additional Advantage ◽  
Analog To Digital ◽  
Split Capacitor

The proposed work presents a High speed 14-bit 125MS/s successive-approximation-register asynchronous analog-to-digital-converter (SAR-ADC). A novel-based Dual-Split-Array-Three-Section (DSATS) capacitor DAC (DSATS-CDAC) is employed to increase the linearity and energy efficiency of the digital-to-analog converter (DAC), additional advantage of this work is that, the area is reduced by 59.76% of conventional design. The proposed switching technique of the (DSATS-CDAC) consumes less switching energy. Additionally, bootstrap switching is employed to ensure improved linearity and reduced power consumption.in order to enhance the speed of operation and increase the precision a preamplifier latch based comparator is implemented with the delay of 250ps. The proposed SAR-ADC prototype is implemented in a 90nm CMOS process and consumes a power of 42.8mW at 1V operating supply. The proposed design achieves a figure of merit (FOM) of 37.43 fJ/conversion-step, signal-to-noise-ratio (SNR) of 81 dB, and an effective-number-of-bits (ENOB) of 13.16 bits with a sampling rate of 125MS/s.

scholarly journals A Design of Low-Power 10-bit 1-MS/s Asynchronous SAR ADC for DSRC Application

Electronics ◽  
2020 ◽  
Vol 9 (7) ◽  
pp. 1100
Author(s):  
Deeksha Verma ◽  
Khuram Shehzad ◽  
Danial Khan ◽  
Sung Jin Kim ◽  
Young Gun Pu ◽  
...  
Keyword(s):  
Low Power ◽  
Sampling Rate ◽  
Complementary Metal Oxide Semiconductor ◽  
Sar Adc ◽  
Oxide Semiconductor ◽  
Digital To Analog Converter ◽  
Analog To Digital ◽  
Clock Generation ◽  
Analog Converter ◽  
Asynchronous Sar

A design of low-power 10-bit 1 MS/s asynchronous successive approximation register analog-to-digital converter (SAR ADC) is presented in this paper. To improve the linearity of the digital-to-analog converter (DAC) and energy efficiency, a common mode-based monotonic charge recovery (CMMC) switching technique is proposed. The proposed switching technique consumes only 63.75 CVREF2 switching energy, which is far less as compared to the conventional switching technique without dividing or adding additional switches. In addition, bootstrap switching is implemented to ensure enhanced linearity. To reduce the power consumption from the comparator, a dynamic latch comparator with a self-comparator clock generation circuit is implemented. The proposed prototype of the SAR ADC is implemented in a 55 nm CMOS (complementary metal-oxide-semiconductor) process. The proposed architecture achieves a figure of merit (FOM) of 17.4 fJ/conversion, signal-to-noise distortion ratio (SNDR) of 60.39 dB, and an effective number of bits (ENOB) of 9.74 bits with a sampling rate of 1 MS/s at measurement levels. The implemented SAR ADC consumes 14.8 µW power at 1 V power supply.

A Noise Reduction 12-bit 125-MSPS SAR ADC with Modified Asynchronous Logic Regulation Technique

2020 ◽  
pp. 2150040
Author(s):  
Daiguo Xu ◽  
Han Yang ◽  
Xing Sheng ◽  
Ting Sun ◽  
Guangbing Chen ◽  
...  
Keyword(s):  
Noise Reduction ◽  
Feedback Loop ◽  
Cmos Technology ◽  
Sar Adc ◽  
Dynamic Comparator ◽  
Digital To Analog Converter ◽  
Analog To Digital ◽  
Asynchronous Logic ◽  
Analog Converter ◽  
Nyquist Rate

This paper presents noise reduction and modified asynchronous logic regulation techniques used in successive approximation register (SAR) analog-to-digital converter (ADC). With a transconductance enhanced structure, noise reduction is provided in the dynamic comparator. The input referred noise of the proposed comparator is about 165[Formula: see text][Formula: see text]V rms at 60∘C (typical corner). An enhanced-positive-feedback loop is introduced to reduce the regeneration delay of the comparator. In addition, a modified asynchronous logic regulation technique is exhibited, a clock with adaptable delay is driving the comparator in approximation phase. Consequently, the settling accuracy of DAC (Digital-to-Analog Converter) is enough and the conversion speed of SAR ADC is increased without any redundant cycles. To demonstrate the proposed techniques, a design of SAR ADC is fabricated in 65-nm CMOS technology, consuming 4[Formula: see text]mW from 1.2[Formula: see text]V power supply with a [Formula: see text][Formula: see text]dB and [Formula: see text][Formula: see text]dB. The proposed ADC core occupies an active area of 0.048[Formula: see text]mm2, and the corresponding FoM is 27.2[Formula: see text]fJ/conversion-step at Nyquist rate.

scholarly journals Noise shaping in SAR ADC

2020 ◽  
Vol 33 (1) ◽  
pp. 15-26
Author(s):  
Dmitry Osipov ◽  
Aleksandr Gusev ◽  
Vitaly Shumikhin ◽  
Steffen Paul
Keyword(s):  
Power Efficiency ◽  
Sampling Rate ◽  
Complementary Metal Oxide Semiconductor ◽  
Sar Adc ◽  
Oxide Semiconductor ◽  
Noise Shaping ◽  
Digital To Analog Converter ◽  
Analog To Digital ◽  
Noise Transfer Function ◽  
Adc Architectures

The successive approximation register (SAR) analog-to-digital converter (ADC) is currently the most popular type of ADC architecture, owing to its power efficiency. They are also used in multichannel systems, where power efficiency is of high importance because of the large number of simultaneously working channels. However, the SAR ADC architecture is not the most area efficient. In SAR ADCs, the binary weighted capacitive digital-to-analog converter (DAC) is used, which means that one additional bit of resolution costs double the increase of area. Oversampling and noise shaping are methods that allow an increase in resolution without an increase of area. In this paper we present the new SAR ADC architectures with a noise shaping. A first-order noise transfer function (NTF) with zero located nearly at one can be achieved. We propose two modifications of the architecture: with zero-only NTF and with the NTF with additional pole. The additional pole theoretically increases the efficiency of noise shaping to further 3 dB. The architectures were applied to the design of SAR ADCs in a 65 nm complementary metal-oxide semiconductor (CMOS) with OSR equal to 10. A 6-bit capacitive DAC was used. The proposed architectures provide nearly 4 additional bits in ENOB. The equalent input bandwitdth is equal to 200 kHz with the sampling rate equal to 4 MS/s.

scholarly journals A Single-Amplifier Dual-Residue Pipelined-SAR ADC

Electronics ◽  
2021 ◽  
Vol 10 (4) ◽  
pp. 421
Author(s):  
Min-Jae Seo
Keyword(s):  
Dynamic Range ◽  
Sampling Rate ◽  
Cmos Technology ◽  
Open Loop ◽  
Sar Adc ◽  
Total Power ◽  
Control Logic ◽  
Analog To Digital ◽  
The One ◽  
And Control

This work presents a 12 bit 200 MS/s dual-residue pipelined successive approximation registers (SAR) analog-to-digital converter (ADC) with a single open-loop residue amplifier (RA). By using the inherent characteristics of the SAR conversion scheme, the proposed ADC sequentially generates two residue levels from the single RA, which eliminates the need for inter-stage gain-matching calibration. To convert the sequentially generated the two residues, a capacitive interpolating SAR ADC (I-SAR ADC) is also proposed. The I-SAR ADC is very compact because it consists of the one comparator, a CDAC, and control logic like a conventional SAR ADC. In addition, the I-SAR ADC needs no static power dissipation for the residue interpolation. A prototype ADC fabricated in a 40 nm CMOS technology occupies an active area of 0.026 mm2. At a 200 MS/s sampling-rate with the Nyquist input, the ADC achieves an SNDR (Signal-to-Noise distortion ratio) of 62.1 dB and 67.1 dB SFDR (Spurious-Free Dynamic Range), respectively. The total power consumed is 3.9 mW under a 0.9 V supply. Without any inter-stage mismatch calibration, the ADC achieve Walden Figure-of-Merit (FoM) of 19.0 fJ/conversion-step.

scholarly journals Implementation of a digital trim scheme for SAR ADCs

2013 ◽  
Vol 11 ◽  
pp. 227-230
Author(s):  
J. Bialek ◽  
A. Wickmann ◽  
F. Ohnhaeuser ◽  
G. Fischer ◽  
R. Weigel ◽  
...  
Keyword(s):  
Transfer Function ◽  
Power Consumption ◽  
Successive Approximation ◽  
Sar Adc ◽  
Production Test ◽  
Digital To Analog Converter ◽  
Analog To Digital ◽  
Capacitor Array ◽  
Capacitor Mismatch ◽  
Analog Converter

Abstract. Successive approximation register (SAR) analog-to-digital Converters (ADC) are based on a capacitive digital-to-analog converter (CDAC) (McCreary and Gray, 1975). The capacitor mismatch in the capacitor array of the CDAC impacts the differential non-linearity (DNL) of the ADC directly. In order to achieve a transfer function without missing codes, trimming of the capacitor array becomes necessary for SAR ADCs with a resolution of more than 12 bit. This article introduces a novel digital approach for trimming. DNL measurements of an 18 bit SAR ADC show that digital trimming allows the same performance as analog trimming. Digital trimming however reduces the power consumption of the ADC, the die size and the required time for the production test.

A 8GHz Differential Comparator for Ultra High Speed ADC in 90nm CMOS Technology

2014 ◽  
Vol 513-517 ◽  
pp. 4572-4575
Author(s):  
Zhong Ying Zhu ◽  
Hui Hong ◽  
Shi Liang Li
Keyword(s):  
High Speed ◽  
Sampling Rate ◽  
Cmos Technology ◽  
Digital Converter ◽  
Analog To Digital ◽  
Fully Differential ◽  
Offset Voltage ◽  
High Speed Adc ◽  
Sine Signal ◽  
Low Offset

A high speed, low offset fully differential comparator for high-speed analog-to-digital converter which can work at a sampling rate of 8GS/s is presented in this paper. The three-stage pre-amplifiers in the improved comparator structure is proposed to ameliorate its gain. The positive feedback regeneration circuit and the improved output buffer are used to ameliorate the comparator bandwidth. Operating with an input sine signal of 1GHz frequency, the circuit can oversample up to 8GS/s with 5bits of resolution. The simulated offset voltage of the comparator by Monte Carlo at 8GHz clock is 5.09mV.

A Linearity Improved 10-bit 120-MS/s 1.5 mW SAR ADC with High-Speed and Low-Noise Dynamic Comparator Technique

2019 ◽  
Vol 29 (06) ◽  
pp. 2050084
Author(s):  
Daiguo Xu ◽  
Hequan Jiang ◽  
Dongbin Fu ◽  
Xiaoquan Yu ◽  
Shiliu Xu ◽  
...  
Keyword(s):  
High Speed ◽  
Cmos Technology ◽  
Low Noise ◽  
Sar Adc ◽  
Dynamic Comparator ◽  
Analog To Digital ◽  
Input Noise ◽  
Clock Feedthrough ◽  
Threshold Voltages ◽  
Coupled Technique

This paper presents a linearity improved 10-bit 120-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with high-speed and low-noise dynamic comparator. A gate cross-coupled technique is introduced in boost sampling switch, the clock feedthrough effect is compensated without extra auxiliary switch and the linearity of sampling switch is enhanced. Further, substrate voltage boost technique is proposed, the absolute values of threshold voltage and equivalent impedances of MOSFETs are both depressed. Consequently, the delay of comparator is also reduced. Moreover, the reduction of threshold voltages for input MOSFETs could bring higher transconductance and lower equivalent input noise. To demonstrate the proposed techniques, a design of SAR ADC is fabricated in 65-nm CMOS technology, consuming 1.5[Formula: see text]mW from 1[Formula: see text]V power supply with a SNDR [Formula: see text][Formula: see text]dB and SFDR [Formula: see text][Formula: see text]dB. The proposed ADC core occupies an active area of 0.021[Formula: see text]mm2, and the corresponding FoM is 24.4 fJ/conversion-step with Nyquist frequency.

An Encoder Used in an Ultra High-Speed Folding and Interpolating ADC

2014 ◽  
Vol 1049-1050 ◽  
pp. 687-690
Author(s):  
Yu Han Gao ◽  
Ru Zhang Li ◽  
Dong Bing Fu ◽  
Yong Lu Wang ◽  
Zheng Ping Zhang
Keyword(s):  
High Speed ◽  
Binary Code ◽  
Sampling Rate ◽  
Gray Code ◽  
Cmos Technology ◽  
Careful Consideration ◽  
Analog To Digital ◽  
Interleaved Adc ◽  
Time Interleaved ◽  
Error Suppression

High speed encoder is the key element of high speed analog-to-digital converter (ADC). Therefor the type of encoder, the type of code, bubble error suppression and bit synchronization must be taken into careful consideration especially for folding and interpolating ADC. To reduce the bubble error which may resulted from the circuit niose, comparator metastability and other interference, the output of quantizer is first encoded with gray code and then converted to binary code. This high speed encoder is verified in the whole time-interleaved ADC with 0.18 Bi-CMOS technology, the whole ADC can achieve a SNR of 45 dB at the sampling rate of 5GHz and input frequency of 495MHz, meanwhile a bit error rate (BER) of less than 10-16 is ensured by this design.

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