scholarly journals A Single-Amplifier Dual-Residue Pipelined-SAR ADC

Electronics ◽  
2021 ◽  
Vol 10 (4) ◽  
pp. 421
Author(s):  
Min-Jae Seo
Keyword(s):  
Dynamic Range ◽  
Sampling Rate ◽  
Cmos Technology ◽  
Open Loop ◽  
Sar Adc ◽  
Total Power ◽  
Control Logic ◽  
Analog To Digital ◽  
The One ◽  
And Control

This work presents a 12 bit 200 MS/s dual-residue pipelined successive approximation registers (SAR) analog-to-digital converter (ADC) with a single open-loop residue amplifier (RA). By using the inherent characteristics of the SAR conversion scheme, the proposed ADC sequentially generates two residue levels from the single RA, which eliminates the need for inter-stage gain-matching calibration. To convert the sequentially generated the two residues, a capacitive interpolating SAR ADC (I-SAR ADC) is also proposed. The I-SAR ADC is very compact because it consists of the one comparator, a CDAC, and control logic like a conventional SAR ADC. In addition, the I-SAR ADC needs no static power dissipation for the residue interpolation. A prototype ADC fabricated in a 40 nm CMOS technology occupies an active area of 0.026 mm2. At a 200 MS/s sampling-rate with the Nyquist input, the ADC achieves an SNDR (Signal-to-Noise distortion ratio) of 62.1 dB and 67.1 dB SFDR (Spurious-Free Dynamic Range), respectively. The total power consumed is 3.9 mW under a 0.9 V supply. Without any inter-stage mismatch calibration, the ADC achieve Walden Figure-of-Merit (FoM) of 19.0 fJ/conversion-step.

scholarly journals A 5GS/s 8-bit ADC with Self-Calibration in 0.18 μm SiGe BiCMOS Technology

Electronics ◽  
2019 ◽  
Vol 8 (2) ◽  
pp. 253
Author(s):  
Dong Wang ◽  
Jian Luan ◽  
Xuan Guo ◽  
Lei Zhou ◽  
Danyu Wu ◽  
...  
Keyword(s):  
Dynamic Range ◽  
Dynamic Performance ◽  
Open Loop ◽  
Total Power ◽  
Least Significant Bit ◽  
Analog To Digital ◽  
Self Calibration ◽  
Differential Nonlinearity ◽  
Bicmos Technology ◽  
Sige Bicmos

A 5 GS/s 8-bit analog-to-digital converter (ADC) implemented in 0.18 μm SiGe BiCMOS technology has been demonstrated. The proposed ADC is based on two-channel time-interleaved architecture, and each sub-ADC employs a two-stage cascaded folding and interpolating topology of radix-4. An open loop track-and-hold amplifier with enhanced linearity is designed to meet the dynamic performance requirement. The on-chip self-calibration technique is introduced to compensate the interleaving mismatches between two sub-ADCs. Measurement results show that the spurious free dynamic range (SFDR) stays above 44.8 dB with a peak of 53.52 dB, and the effective number of bits (ENOB) is greater than 5.8 bit with a maximum of 6.97 bit up to 2.5 GS/s. The ADC exhibits a differential nonlinearity (DNL) of -0.31/+0.23 LSB (least significant bit) and an integral nonlinearity (INL) of -0.68/+0.68 LSB, respectively. The chip occupies an area of 3.9 × 3.6 mm2, consumes a total power of 2.8 W, and achieves a figure of merit (FoM) of 10 pJ/conversion step.

Area-Efficient Capacitor-Splitting Switching Scheme with a Nearly Constant Common-Mode Voltage for SAR ADCs

2019 ◽  
Vol 29 (10) ◽  
pp. 2020005
Author(s):  
Hao Wang ◽  
Wenming Xie ◽  
Zhixin Chen
Keyword(s):  
Dynamic Range ◽  
Supply Voltage ◽  
Sampling Rate ◽  
Cmos Technology ◽  
Switching Scheme ◽  
Common Mode ◽  
Analog To Digital ◽  
Common Mode Voltage ◽  
Switching Method ◽  
Area Efficient

A novel area-efficient switching scheme is proposed for the successive approximation register (SAR) analog-to-digital converters (ADCs). The capacitor-splitting structure, charge-average switching technique, and [Formula: see text] (equal to [Formula: see text]/4) are combined together and optimized to realize the proposed switching scheme. [Formula: see text] is only used in the last two bit cycles, which affects the ADC accuracy little and reduces capacitor area by half. It achieves a 98% less switching energy and an 87.5% less capacitor area compared with the conventional switching method. In addition, the DAC output common-mode voltage is approximately constant. Thus, the proposed switching method is a good tradeoff among power consumption, capacitor area, DAC output common-mode voltage, and ADC accuracy. The proposed SAR ADC is simulated in 0.18[Formula: see text][Formula: see text]m CMOS technology with a supply voltage of 0.6[Formula: see text]V and at a sampling rate of 20[Formula: see text]kS/s. The signal-to-noise-distortion ratio (SNDR) and spurious free dynamic range (SFDR) are 58.2 and 73.7[Formula: see text]dB, respectively. The effective number of bits (ENOB) is 9.4. It consumes 42[Formula: see text]nW, resulting in a figure-of-merit (FoM) of 3.11 fJ/conversion-step.

Design of Low Power and High Precision Successive Approximation Register Analog-to-Digital Converter (SAR-ADC) Based on Piecewise Capacitance and Calibration Technique

2020 ◽  
Vol 15 (4) ◽  
pp. 478-486
Author(s):  
Sheng-Biao An ◽  
Li-Xin Zhao ◽  
Shi-Cong Yang ◽  
Tao An ◽  
Rui-Xia Yang
Keyword(s):  
Power Consumption ◽  
Successive Approximation ◽  
Dynamic Range ◽  
Sar Adc ◽  
Total Power ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Analog To Digital ◽  
Successive Approximation Register ◽  
Total Power Consumption

This paper presents a charge redistributed successive approximation register analog-to-digital converter (SAR ADC). Compared with the traditional Digital-Analog Convertor (DAC), the power consumption of the DAC scheme is reduced by 90%, the area is reduced by 60%. The test chip fabricated in 180 nm Complementary Metal Oxide Semiconductor (CMOS) occupied an active area of 0.12 mm 2 . At 10 MS/s, a signal-to-noise and distortion ratio (SNDR) of 57.70 dB and a spurious-free dynamic range (SFDR) of 55.63 dB are measured with 1.68 Vpp differential-mode input signal. The total power consumption is 690 μW corresponding to 67 fJ/conversion step figure of merit.

Design of Low Voltage Low Power ADC for WSN Node

2013 ◽  
Vol 760-762 ◽  
pp. 561-566
Author(s):  
Si Kui Ren ◽  
Zhi Qun Li
Keyword(s):  
Low Power ◽  
Figure Of Merit ◽  
Dynamic Range ◽  
Low Voltage ◽  
Cmos Technology ◽  
Total Power ◽  
Chip Area ◽  
Analog To Digital ◽  
Spurious Free Dynamic Range ◽  
Free Dynamic

This paper presents a low power low voltage 7bit 16MS/s SAR ADC (successive approximation register analog-to-digital converter) for the application of ZigBee receiver. The proposed 7-bit ADC is designed and simulated in 180nm RF CMOS technology. Post simulation results show that at 1.0-V supply and 16 MS/s, the ADC achieves a SNDR (signal-to-noise-and-distortion ratio) and SFDR (Spurious Free Dynamic Range) are 43.6dB, 57.4dB respectively. The total power dissipation is 228μW, and it occupies a chip area of 0.525 mm2. It results in a figure-of-merit (FOM) of 0.11pJ/step.

scholarly journals A 14-bit High Speed 125MS/s Low Power SAR ADC using Dual Split Capacitor DAC Architecture in 90nm CMOS Technology

2021 ◽  
Vol 15 ◽  
pp. 556-568
Author(s):  
Chaya Shetty ◽  
M. Nagabushanam ◽  
Venkatesh Nuthan Prasad
Keyword(s):  
High Speed ◽  
Signal To Noise Ratio ◽  
Sampling Rate ◽  
Cmos Technology ◽  
Sar Adc ◽  
Cmos Process ◽  
Digital To Analog Converter ◽  
Additional Advantage ◽  
Analog To Digital ◽  
Split Capacitor

The proposed work presents a High speed 14-bit 125MS/s successive-approximation-register asynchronous analog-to-digital-converter (SAR-ADC). A novel-based Dual-Split-Array-Three-Section (DSATS) capacitor DAC (DSATS-CDAC) is employed to increase the linearity and energy efficiency of the digital-to-analog converter (DAC), additional advantage of this work is that, the area is reduced by 59.76% of conventional design. The proposed switching technique of the (DSATS-CDAC) consumes less switching energy. Additionally, bootstrap switching is employed to ensure improved linearity and reduced power consumption.in order to enhance the speed of operation and increase the precision a preamplifier latch based comparator is implemented with the delay of 250ps. The proposed SAR-ADC prototype is implemented in a 90nm CMOS process and consumes a power of 42.8mW at 1V operating supply. The proposed design achieves a figure of merit (FOM) of 37.43 fJ/conversion-step, signal-to-noise-ratio (SNR) of 81 dB, and an effective-number-of-bits (ENOB) of 13.16 bits with a sampling rate of 125MS/s.

scholarly journals A Novel Built-in Self Calibration Technique to Minimize Capacitor Mismatch for 12-bit 32MS/s SAR ADC

2015 ◽  
Vol 10 (3) ◽  
pp. 187-200
Author(s):  
Inseok Jung ◽  
Kyung Ki Kim ◽  
Yong-Bin Kim
Keyword(s):  
Sampling Rate ◽  
Cmos Technology ◽  
Sar Adc ◽  
Digital To Analog Converter ◽  
Analog To Digital ◽  
Self Calibration ◽  
Conventional Procedure ◽  
Offset Voltage ◽  
Capacitor Mismatch ◽  
Voltage Amplifier

This paper proposes a novel Built-in Self Calibration (BISC) technique for a 12-bit 32MS/s successive approximation register (SAR) analog-to-digital converter (ADC) using a single input to reduce the capacitor mismatch of the digital-to-analog converter (DAC) and to compensate the comparator input offset voltage. The proposed self-calibration scheme optimize the mismatch of the DAC by changing additional auxiliary capacitor array during calibration mode. In addition, in order to minimize the offset voltage of the comparator in the SAR ADC, a simplified voltage amplifier is proposed. The controller for the proposed algorithm operates as foreground operation to achieve low power consumption during operation. Compared to the converters that use the conventional procedure, INL and DNL are reduced by about 47% and 52%, respectively. The prototype was designed using 130nm single poly 6 metal standard CMOS technology. The ADC achieves a SNDR of 65.6 dB and consumes 4.62 mW. The ADC core occupies an active area of only 240μmÍ 298 μm using 1.2V supply and the sampling rate of 50 MS/s.

scholarly journals Design an Improved Structure for 10-Bit Pipeline Analog to Digital Converter Based on 0.18µm CMOS Technology

2019 ◽  
Vol 9 (2) ◽  
pp. 169-176
Author(s):  
Arash Rezapour ◽  
Farbod Setoudeh ◽  
Mohammad Bagher Tavakoli
Keyword(s):  
Data Transfer ◽  
Input Voltage ◽  
Cmos Technology ◽  
Open Loop ◽  
Total Power ◽  
Analog To Digital ◽  
Second Stage ◽  
Novel Structure ◽  
Total Power Consumption ◽  
Two Stages

Abstract This paper proposed a novel structure of a 10-bit, 400MS/s pipelined analog to digital convertor using 0.18 µm TSMC technology. In this paper, two stages are used to converter design and a new method is proposed to increase the speed of the pipeline analog to digital convertor. For this purpose, the amplifier is not used at the first stage and the buffer is used for data transfer to the second stage, in the second stage an amplifier circuit with accurate gain of 8 that is open loop with a new structure was used to speed up, also the design is such that the first 4 bits are extracted simultaneously with sampling. On the other hand, in this structure, since in the first stage the information is not amplified and transferred to the second stage, the accuracy of the comparator circuit should be high, therefore a new structure is proposed to design a comparator circuit that can detect unwanted offsets and eliminate them without delay, and thus can detect the smallest differences in input voltage. The proposed analog to digital convertor was designed with a resolution of 10 bits and a speed of 400MS/s, with the total power consumption 74.3mW using power supply of 1.8v.

SELF-TIMED ARCHITECTURE FOR MASKED SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERSION

2007 ◽  
Vol 16 (01) ◽  
pp. 1-14
Author(s):  
TASKIN KOCAK ◽  
GEORGE R. HARRIS ◽  
RONALD F. DEMARA
Keyword(s):  
Successive Approximation ◽  
Cmos Technology ◽  
Digital Systems ◽  
Digital Converter ◽  
Digital Conversion ◽  
Analog To Digital ◽  
Analog Signals ◽  
Analog To Digital Conversion ◽  
Null Convention Logic ◽  
The One

In this paper, a novel architecture for self-timed analog-to-digital conversion is presented and designed using the NULL Convention Logic (NCL) paradigm. This analog-to-digital converter (ADC) employs successive approximation and a one-hot encoded masking technique to digitize analog signals. The architecture scales readily to any given resolution by utilizing the one-hot encoded scheme to permit identical logical components for each bit of resolution. The four-bit configuration of the proposed design has been implemented and assessed via simulation in 0.18-μm CMOS technology. Furthermore, the ADC may be interfaced with either synchronous or four-phase asynchronous digital systems.

A Linearity Improved 10-bit 120-MS/s 1.5 mW SAR ADC with High-Speed and Low-Noise Dynamic Comparator Technique

2019 ◽  
Vol 29 (06) ◽  
pp. 2050084
Author(s):  
Daiguo Xu ◽  
Hequan Jiang ◽  
Dongbin Fu ◽  
Xiaoquan Yu ◽  
Shiliu Xu ◽  
...  
Keyword(s):  
High Speed ◽  
Cmos Technology ◽  
Low Noise ◽  
Sar Adc ◽  
Dynamic Comparator ◽  
Analog To Digital ◽  
Input Noise ◽  
Clock Feedthrough ◽  
Threshold Voltages ◽  
Coupled Technique

This paper presents a linearity improved 10-bit 120-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with high-speed and low-noise dynamic comparator. A gate cross-coupled technique is introduced in boost sampling switch, the clock feedthrough effect is compensated without extra auxiliary switch and the linearity of sampling switch is enhanced. Further, substrate voltage boost technique is proposed, the absolute values of threshold voltage and equivalent impedances of MOSFETs are both depressed. Consequently, the delay of comparator is also reduced. Moreover, the reduction of threshold voltages for input MOSFETs could bring higher transconductance and lower equivalent input noise. To demonstrate the proposed techniques, a design of SAR ADC is fabricated in 65-nm CMOS technology, consuming 1.5[Formula: see text]mW from 1[Formula: see text]V power supply with a SNDR [Formula: see text][Formula: see text]dB and SFDR [Formula: see text][Formula: see text]dB. The proposed ADC core occupies an active area of 0.021[Formula: see text]mm2, and the corresponding FoM is 24.4 fJ/conversion-step with Nyquist frequency.

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