Detecting Power Shorts from Front and Backside of IC Packages Using Scanning SQUID Microscopy

1999 ◽  
Author(s):  
L. A. Knauss ◽  
B. M. Frazier ◽  
H. M. Christen ◽  
S. D. Silliman ◽  
K. S. Harshavardhan ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Integrated Circuit ◽  
Quantum Interference ◽  
Flip Chip ◽  
Near Field ◽  
Current Density Distribution ◽  
Scanning Squid ◽  
Tools And Techniques ◽  
The Magnetic Field

Abstract As process technologies of integrated circuits become more complex and the industry moves toward flipchip packaging, present tools and techniques are having increasing difficulty in meeting failure analysis needs. One of the most common failures in these types of ICs and packages is power shorts, both during fabrication and in the field. Many techniques such as Emission Microscopy and Liquid Crystal are either not able to locate power shorts or are inhibited in their effectiveness by multiple layers of metal and flip-chip type packaging. A scanning SQUID microscope can overcome some of these difficulties. A SQUID (Superconducting Quantum Interference Device) is a very sensitive magnetic sensor that can image magnetic fields generated by magnetic materials or currents (such as those in an integrated circuit). The current density distribution in the sample can then be calculated from the magnetic field image, and resolutions approaching 5 times the near field limit can be obtained. We present here the application of a SQUID microscope to physical failure analysis and compare it with other techniques to detect shorted current paths in flip-chip mounted ICs and packages.

Failure Analysis of Short Faults on Advanced Wire-Bond and Flip-Chip Packages with Scanning SQUID Microscopy

2004 ◽  
Author(s):  
Steve K. Hsiung ◽  
Kevan V. Tan ◽  
Andrew J. Komrowski ◽  
Daniel J. D. Sullivan ◽  
Jan Gaudestad
Keyword(s):  
Magnetic Fields ◽  
Integrated Circuits ◽  
Quantum Interference ◽  
Flip Chip ◽  
Infrared Emission ◽  
Fault Analysis ◽  
Wire Bond ◽  
Overlay Design ◽  
Scanning Squid ◽  
Metal Layers

Abstract Scanning SQUID (Superconducting Quantum Interference Device) Microscopy, known as SSM, is a non-destructive technique that detects magnetic fields in Integrated Circuits (IC). The magnetic field, when converted to current density via Fast Fourier Transform (FFT), is particularly useful to detect shorts and high resistance (HR) defects. A short between two wires or layers will cause the current to diverge from the path the designer intended. An analyst can see where the current is not matching the design, thereby easily localizing the fault. Many defects occur between or under metal layers that make it impossible using visible light or infrared emission detecting equipment to locate the defect. SSM is the only tool that can detect signals from defects under metal layers, since magnetic fields are not affected by them. New analysis software makes it possible for the analyst to overlay design layouts, such as CAD Knights, directly onto the current paths found by the SSM. In this paper, we present four case studies where SSM successfully localized short faults in advanced wire-bond and flip-chip packages after other fault analysis methods failed to locate the defects.

Localization of Dead Open in a Solder Bump by Space Domain Reflectometry

2012 ◽  
Author(s):  
David P. Vallett ◽  
Daniel A. Bader ◽  
Vladimir V. Talanov ◽  
Jan Gaudestad ◽  
Nicolas Gagliolo ◽  
...  
Keyword(s):  
Magnetic Field ◽  
Failure Analysis ◽  
Quantum Interference ◽  
Flip Chip ◽  
Solder Bump ◽  
Frequency Range ◽  
Superconducting Quantum Interference Device ◽  
Space Domain ◽  
Non Destructive ◽  
The Magnetic Field

Abstract Space Domain Reflectometry (SDR) is a newly developed non-destructive failure analysis (FA) technique for localizing open defects in both packages and dies through mapping in space domain the magnetic field produced by a radio frequency (RF) current induced in the sample, herein the name Space Domain Reflectometry. The technique employs a scanning superconducting quantum interference device (SQUID) RF microscope operating over a frequency range from 60 to 200 MHz. In this paper we demonstrate that SDR is capable of locating defective micro bumps in a flip-chip device.

scholarly journals Die Backside FIB Preparation for Identification and Characterization of Metal Voids

1999 ◽  
Author(s):  
Ann N. Campbell ◽  
William F. Filter ◽  
Nicholas Antoniou
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Cross Sections ◽  
Integrated Circuit ◽  
Flip Chip ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Milling Process ◽  
Plan View ◽  
Metal Interconnects

Abstract Both the increased complexity of integrated circuits, resulting in six or more levels of integration, and the increasing use of flip-chip packaging have driven the development of integrated circuit (IC) failure analysis tools that can be applied to the backside of the chip. Among these new approaches are focused ion beam (FIB) tools and processes for performing chip edits/repairs from the die backside. This paper describes the use of backside FIB for a failure analysis application rather than for chip repair. Specifically, we used FIB technology to prepare an IC for inspection of voided metal interconnects (“lines”) and vias. Conventional FIB milling was combined with a superenhanced gas assisted milling process that uses XeF2 for rapid removal of large volumes of bulk silicon. This combined approach allowed removal of the TiW underlayer from a large number of M1 lines simultaneously, enabling rapid localization and plan view imaging of voids in lines and vias with backscattered electron (BSE) imaging in a scanning electron microscope (SEM). Sequential cross sections of individual voided vias enabled us to develop a 3D reconstruction of these voids. This information clarified how the voids were formed, helping us identify the IC process steps that needed to be changed.

Backside Fault Isolation Using a Magnetic Field Imaging System on SRAMs with Indirect Shorts

2000 ◽  
Author(s):  
L. A. Knauss ◽  
B. M. Frazier ◽  
A. B. Cawthorne ◽  
E. Budiarto ◽  
R. Crandall ◽  
...  
Keyword(s):  
Magnetic Field ◽  
Integrated Circuit ◽  
Quantum Interference ◽  
Flip Chip ◽  
Imaging System ◽  
Fault Isolation ◽  
Image Subtraction ◽  
Magnetic Field Imaging ◽  
The Magnetic Field ◽  
Field Imaging

Abstract With the arrival of flip-chip packaging, present tools and techniques are having increasing difficulty meeting failure-analysis needs. Recently a magneticfield imaging system has been used to localize shorts in buried layers of both packages and dies. Until now, these shorts have been powered directly through simple connections at the package. Power shorts are examples of direct shorts that can be powered through connections to Vdd and Vss at the package level. While power shorts are common types of failure, equally important are defects such as logic shorts, which cannot be powered through simple package connections. These defects must be indirectly activated by driving the part through a set of vectors. This makes the magnetic-field imaging process more complicated due to the large background currents present along with the defect current. Magnetic-field imaging is made possible through the use of a SQUID (Superconducting Quantum Interference Device), which is a very sensitive magnetic sensor that can image magnetic fields generated by magnetic materials or currents (such as those in an integrated circuit). The current-density distribution in the sample can then be calculated from the magnetic-field image revealing the locations of shorts and other current anomalies. Presented here is the application of a SQUID-based magnetic-field imaging system for isolation of indirect shorts. This system has been used to investigate shorts in two flip-chip-packaged SRAMs. Defect currents as small as 38 μA were imaged in a background of 1 A. The measurements were made using a lock-in thechnique and image subtraction. The magnetic-field image from one sample is compared with the results from a corresponding infrared-microscope image.

Failure Analysis of Sub-Micron Semiconductor Integrated Circuit Using Backside Photon Emission Microscopy

1999 ◽  
Author(s):  
Soon Lim ◽  
Jian Hua Bi ◽  
Lian Choo Goh ◽  
Soh Ping Neo ◽  
Sudhindra Tatti
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Integrated Circuit ◽  
Flip Chip ◽  
Photon Emission ◽  
Fault Isolation ◽  
Integrated Circuit Fabrication ◽  
Circuit Fabrication ◽  
Emission Microscopy ◽  
On Chip

Abstract The progress of modern day integrated circuit fabrication technology and packaging has made fault isolation using conventional emission microscopy via the top of the integrated circuit more difficult, if not impossible. This is primarily due to the use of increased levels and density of metal-interconnect, and the advent of new packaging technology, e.g. flip-chip, ball-grid array and lead-on-chip, etc. Backside photon emission microscopy, i.e. performing photon emission microscopy through the bulk of the silicon via the back of the integrated circuit is a solution to this problem. This paper outlines the failure analysis of sub-micron silicon integrated circuits using backside photon emission microscopy. Sample preparation, practical difficulties encountered and case histories will be discussed.

Super-Conducting Quantum Interference Device Technique: 3-D Localization of a Short within a Flip Chip Assembly

2001 ◽  
Author(s):  
Kendall Scott Wills ◽  
Omar Diaz de Leon ◽  
Kartik Ramanujachar ◽  
Charles P. Todd
Keyword(s):  
Form Factor ◽  
Failure Analysis ◽  
Time Domain ◽  
Quantum Interference ◽  
Flip Chip ◽  
Time Domain Reflectometry ◽  
Interfacial Region ◽  
Precise Localization ◽  
Super Conducting ◽  
Accuracy Of Measurement

Abstract In the current generations of devices the die and its package are closely integrated to achieve desired performance and form factor. As a result, localization of continuity failures to either the die or the package is a challenging step in failure analysis of such devices. Time Domain Reflectometry [1] (TDR) is used to localize continuity failures. However the accuracy of measurement with TDR is inadequate for effective localization of the failsite. Additionally, this technique does not provide direct 3-Dimenstional information about the location of the defect. Super-conducting Quantum Interference Device (SQUID) Microscope is useful in localizing shorts in packages [2]. SQUID microscope can localize defects to within 5um in the X and Y directions and 35um in the Z direction. This accuracy is valuable in precise localization of the failsite within the die, package or the interfacial region in flipchip assemblies.

Interfacial Delamination in Plastic Encapsulated Integrated Circuits (Pics)

1996 ◽  
Vol 445 ◽  
Author(s):  
Nickolaos Strifas ◽  
Aris Christou
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Stress Corrosion ◽  
Integrated Circuit ◽  
Point Of View ◽  
Acoustic Microscopy ◽  
Electrical Performance ◽  
Premature Failure ◽  
Interfacial Delamination ◽  
Die Surface

AbstractThe reliability of plastic packaged integrated circuits was assessed from the point of view of interfacial mechanical integrity. It is shown that the effect of structural weaknesses caused by poor bonding, voids, microcracks or delamination may not be evident in the electrical performance characteristics, but may cause premature failure. Acoustic microscopy (C-SAM) was selected for nondestructive failure analysis of the plastic integrated circuit (IC) packages. Integrated circuits in plastic dual in line packages were initially subjected to temperature (25 °C to 85 °C) and humidity cycling (50 to 85 %) where each cycle was of one hour duration and for over 100 cycles and then analyzed. Delamination at the interfaces between the different materials within the package, which is a major cause of moisture ingress and subsequent premature package failure, was measured. The principal areas of delamination were found along the leads extending from the chip to the edge of the molded body and along the die surface itself. Images of the 3-D internal structure were produced that were used to determine the mechanism for a package failure. The evidence of corrosion and stress corrosion cracks in the regions of delamination was identified.

Non-Destructive Open Fault Isolation in Flip-Chip Devices with Space-Domain Reflectometry

2013 ◽  
Author(s):  
W. Qiu ◽  
M.S. Wei ◽  
J. Gaudestad ◽  
V.V. Talanov
Keyword(s):  
Quantum Interference ◽  
Flip Chip ◽  
Time Domain Reflectometry ◽  
Fault Isolation ◽  
Superconducting Quantum Interference Device ◽  
Isolation Method ◽  
Space Domain ◽  
Open Faults ◽  
Scanning Squid ◽  
Non Destructive

Abstract Space-domain reflectometry (SDR) utilizing scanning superconducting quantum interference device (SQUID) microscopy is a newly developed non-destructive failure analysis (FA) technique for open fault isolation. Unlike the conventional open fault isolation method, time-domain reflectometry (TDR), scanning SQUID SDR provides a truly two-dimensional physical image of device under test with spatial resolution down to 30 μm [1]. In this paper, the SQUID SDR technique is used to isolate dead open faults in flip-chip devices. The experimental results demonstrate the capability of SDR in open fault detection

Failure Analysis of FinFET Circuitry at GHz Speeds Using Voltage-Contrast and Stroboscopic Techniques on a Scanning Electron Microscope

2019 ◽  
Author(s):  
James Vickers ◽  
Seema Somani ◽  
Blake Freeman ◽  
Pete Carleson ◽  
Lubomír Tùma ◽  
...  
Keyword(s):  
Electron Microscope ◽  
Scanning Electron Microscope ◽  
Integrated Circuits ◽  
Electrical Activity ◽  
Failure Analysis ◽  
Integrated Circuit ◽  
Contrast Mechanism ◽  
Voltage Contrast ◽  
Working Device ◽  
Scanning Electron

Abstract We report on using the voltage-contrast mechanism of a scanning electron microscope to probe electrical waveforms on FinFET transistors that are located within active integrated circuits. The FinFET devices are accessed from the backside of the integrated circuit, enabling electrical activity on any transistor within a working device to be probed. We demonstrate gigahertz-bandwidth probing at 10-nm resolution using a stroboscopic pulsed electron source.

Backside De-Processing of Integrated Circuits 40 nm and Below

2011 ◽  
Author(s):  
Yuanjing Li ◽  
Steven Scott ◽  
Howard Lee Marks
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Flip Chip ◽  
Processing Technique ◽  
Multi Level

Abstract This paper presents a novel backside de-processing technique for effective failure analysis of advanced multi-level interconnect metallization CMOS ICs with flip chip package.

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