Stacked-Die Failure Mechanisms for an Octal, Current Input 20-Bit Analog-to-Digital Converter

2005 ◽  
Author(s):  
Bob K. Craigin ◽  
Bin Ling Zhou ◽  
Jason R. Bridgmon
Keyword(s):  
Failure Analysis ◽  
Failure Mechanisms ◽  
Ion Migration ◽  
Analog To Digital ◽  
Electrical Failure ◽  
Analysis Techniques ◽  
Die Attach ◽  
Current Input ◽  
Self Test ◽  
Package Reliability

Abstract Stacked-die packaging was used to make an octal 20-bit analog-to-digital (A/D) converter by stacking two quad A/D converter die in a single 48-lead QFN (quad flat-pack, no leads) package. Reliability testing for product qualification initially failed only (biased) HAST test. Two failure mechanisms were identified. The first mechanism was silver ion migration at sensitive analog inputs due to high conductive die-attach fillets on the bottom die. The second mechanism was ILD delamination and passivation layer cracking due to spacer-attach stress on the surface of the bottom die. Electrical failure analysis was aided by a self test mode designed into the quad A/D converter. Package opening and other standard failure analysis techniques required some modification to accommodate the stacked-die package. This work points to critical stacked-die assembly steps, including conductive die-attach and nonconductive spacer-attach application, where effects of moisture, bias, and thermal stress must all be considered.

Advanced IR-OBIRCH Analysis Technique for High Isb Failure Analysis

2010 ◽  
Author(s):  
Kuo Hsiung Chen ◽  
Wen Sheng Wu ◽  
Yu Hsiang Shu ◽  
Jian Chan Lin
Keyword(s):  
Failure Analysis ◽  
Failure Mechanisms ◽  
Fault Localization ◽  
Resistance Change ◽  
The Real ◽  
Analysis Techniques ◽  
Analysis Technique ◽  
Leakage Failure ◽  
Failure Site

Abstract IR-OBIRCH (Infrared Ray – Optical Beam Induced Resistance Change) is one of the main failure analysis techniques [1] [2] [3] [4]. It is a useful tool to do fault localization on leakage failure cases such as poor Via or contact connection, FEoL or BEoL pattern bridge, and etc. But the real failure sites associated with the above failure mechanisms are not always found at the OBIRCH spot locations. Sometimes the real failure site is far away from the OBIRCH spot and it will result in inconclusive PFA Analysis. Finding the real failure site is what matters the most for fault localization detection. In this paper, we will introduce one case using deep sub-micron process generation which suffers serious high Isb current at wafer donut region. In this case study a BEoL Via poor connection is found far away from the OBIRCH spots. This implies that layout tracing skill and relation investigation among OBIRCH spots are needed for successful failure analysis.

Coupling C-AFM with Nanoprobing Technique for Further Junction Leakage Analysis

2006 ◽  
Author(s):  
Cha-Ming Shen ◽  
Tsan-Chen Chuang ◽  
Chen-May Huang ◽  
Shi-Chen Lin ◽  
Jie-Fei Chang
Keyword(s):  
Failure Analysis ◽  
Atomic Force Microscope ◽  
Failure Modes ◽  
Electrical Characteristic ◽  
Failure Mechanisms ◽  
Gate Leakage ◽  
Process Technology ◽  
Analysis Techniques ◽  
Atomic Force ◽  
Or Gate

Abstract With the evolution of advanced process technology, failure analysis has become more and more difficult because more defects are of the non-visual type (very tiny or even invisible defects) from new failure mechanisms. In this article, a novel and effective methodology which couples the conductive atomic force microscope (C-AFM) with nano-probing technique is proposed to reveal some particular failure modes which were not observable and difficult to identify with traditional physical failure analysis techniques. The capability of coupling C-AFM with nano-probing technique is used to distinguish cases which suffer general junction leakage or gate leakage from those that form the fake junction leakage or gate leakage cases. C-AFM can detect the abnormal contacts quickly, and nano-probing could provide the precise electrical characteristic further. Then, combining these variant measuring results, the favorable tactics can be adopted to deal with different states.

An Application of Breakthrough Failure Analysis Techniques in Eliminating Silicon Dislocation Problem in Sub-Micron CMOS Devices

1997 ◽  
Author(s):  
E. H. Yeoh ◽  
W. M. Mak ◽  
H. C. Lock ◽  
S. K. Sim ◽  
C. C. Ooi ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Failure Mechanism ◽  
Packing Density ◽  
Failure Mechanisms ◽  
Potential Solution ◽  
Critical Dimensions ◽  
Functional Failure ◽  
Analysis Techniques ◽  
Root Cause ◽  
First Time

Abstract As device interconnect layers increase and transistor critical dimensions decrease below sub-micron to cater for higher speed and higher packing density, various new and subtle failure mechanisms have emerged and are becoming increasingly prevalent. Silicon dislocation is a new failure mechanism that falls in this category and was for the first time, uncovered in submicron multilayered CMOS devices. This mechanism was responsible for a systematic yield problem; identified as the 'centre GFA wafer' functional failure problem. In this paper, several breakthrough failure analysis techniques used to narrow down and identify this new mechanism will be presented. Root cause determination and potential solution to this problem will also be discussed.

Failure Analysis Techniques and Failure Mechanisms Utilizing a Plasma Etcher

1979 ◽  
Author(s):  
J. J. Gajda ◽  
D. J. DeLorenzo ◽  
J. A. Wade
Keyword(s):  
Failure Analysis ◽  
Failure Mechanisms ◽  
Analysis Techniques

Contact Leakage Failure Analysis by EBIC, C-AFM and Nano-probing

2019 ◽  
Author(s):  
Kuang-Tse Ho ◽  
Chien-Wei Wu ◽  
Te-Fu Chang ◽  
Chia-Hsiang Yen ◽  
Ching-Hsiang Chan
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
Failure Mechanisms ◽  
Fault Isolation ◽  
Electrical Failure ◽  
Sem And Tem ◽  
Leakage Failure

Abstract This research sets up failure analysis flow to verify failure mechanisms and root causes of different kinds of contact leakage. This flow mainly uses EBIC, C-AFM and nano-probing to do fault isolation and confirm electrical failure mechanisms. Appropriate sample preparation is also mandatory for FIB, SEM and TEM inspection.

Speed Path Analysis: A Connection Between Speed Degradation, Silicon Dislocations, and Light Induced Voltage Alteration

2003 ◽  
Author(s):  
D. Davis
Keyword(s):  
Failure Analysis ◽  
Path Analysis ◽  
Standard Test ◽  
Induced Voltage ◽  
Test Program ◽  
Electrical Failure ◽  
Analysis Techniques ◽  
Current Voltage

Abstract The failure analyst is often times challenged with the analysis of devices that fail due to speed degradation. These are units that pass the entire standard test program as long as the speed at which the device is tested is kept below a certain level. Many times, these units are binned and sold to customers at reduced prices. The unresolved rate for these types of failures is often sporadic and at times there isn’t any defect that is physically observable or detectable with global EFA (electrical failure analysis) techniques. These devices are usually from an advanced process where a shift in performance such as current, voltage, and speed (frequency) is common.

Signature Analysis of Device Failure Mechanisms on 2.5D Package IC Devices

2016 ◽  
Author(s):  
Daniel C. Nuez
Keyword(s):  
Failure Analysis ◽  
Time Domain ◽  
Failure Mechanisms ◽  
Time Domain Reflectometry ◽  
Device Failure ◽  
Analysis Techniques ◽  
3D Package ◽  
Non Destructive ◽  
Interconnect Technology ◽  
Scanning Acoustic Microscope

Abstract The growing popularity of 2.5D SSIT (Stacked Silicon Interconnect Technology) & 3D package technology in the IC industry had made it more challenging for manufacturers and packaging assembly sites to perform failure analysis and identifying the root causes of failures. There had been some technical papers written on various failure analysis techniques on 2.5D SSIT and 3D IC packages using a variety of equipment for detecting and localizing failures [1, 2]. This paper explains a non-evasive, non-destructive approach of localizing failures on a 2.5D SSIT package by identifying and recognizing certain waveform patterns that the failing devices exhibit in the scanning acoustic microscope A-Scan and in Time domain reflectometry. There are noticeable waveform patterns that an analyst can recognize and used to determine certain types of failure mechanisms that may be present in the device. Please note that it is very important to use the exact same type of package sample when characterizing and comparing waveform patterns as package variability from vendor to vendor and material contents can certainly affect the results.

Accelerating Technology Development and Yield Ramp on First Silicon Utilizing a Wafer-Level Dynamic EFA System

2016 ◽  
Author(s):  
Li-Qing Chen ◽  
Ming-Sheng Sun ◽  
Jui-Hao Chao ◽  
Soon Fatt Ng ◽  
Kapilevich Izak ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Technology Development ◽  
Photon Emission ◽  
Wafer Level ◽  
Success Story ◽  
Electrical Failure ◽  
Analysis Techniques ◽  
Soft Failure ◽  
Scan Chain ◽  
Hard Failure

Abstract This paper presents the success story of the learning process by reporting four cases using four different failure analysis techniques. The cases covered are IDDQ leakage, power short, scan chain hard failure, and register soft failure. Hardware involved in the cases discussed are Meridian WS-DP, a wafer-level electrical failure analysis (EFA) system from DCG Systems, V9300 tester from Advantest, and a custom cable interface integrating WSDP and V9300 with the adaption of direct-probe platform that is widely deployed for SoC CP test. Four debug cases are reported in which various EFA techniques are proven powerful and effective, including photon emission, OBIRCH, Thermal Frequency Imaging, LVI, LVP, and dynamic laser stimulation.

Ultra-Thinning of Silicon for Backside Fault Isolation

2019 ◽  
Author(s):  
M. J. Campin ◽  
P. Nowakowski ◽  
P. E. Fischione
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
State Of The Art ◽  
Fault Isolation ◽  
Infrared Light ◽  
Ion Milling ◽  
Electrical Failure ◽  
Analysis Techniques ◽  
Broad Beam ◽  
Silicon Thickness

Abstract The size of devices on state-of-the-art integrated circuits continues to decrease with each technology node, which drives the need to continually improve the resolution of electrical failure analysis techniques. Solid immersion lenses are commonly used in combination with infrared light to perform analysis from the backside of the device, but typically only have resolutions down to ~200 nm. Improving resolution beyond this requires the use of shorter wavelengths, which in turn requires a silicon thickness in the 2 to 5 µm range. Current ultra-thinning techniques allow consistent thinning to ~10 µm. Thinning beyond this, however, has proven challenging. In this work, we show how broad beam Ar ion milling can be used to locally thin a device’s backside silicon until the remaining silicon thickness is < 5 µm.

Novel Failure Analysis Sample Preparation Techniques for PoP Packaging

2012 ◽  
Author(s):  
Ng Sea Chooi ◽  
Chor Theam Hock ◽  
Ma Choo Thye ◽  
Khoo Poh Tshin ◽  
Dan Bockelman
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
Failure Mechanisms ◽  
Preparation Process ◽  
Space Saving ◽  
Optical Probing ◽  
Preparation Techniques

Abstract Trends in the packaging of semiconductors are towards miniaturization and high functionality. The package-on-package(PoP) with increasing demands is beneficial in cost and space saving. The main failure mechanisms associated with PoP technology, including open joints and warpage, have created a lot of challenges for Assembly and Failure Analysis (FA). This paper outlines the sample preparation process steps to overcome the challenges to enable successful failure analysis and optical probing.

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