Effectiveness of Emission Microscopy in the Failure Analysis of CMOS ASIC Devices

1997 ◽  
Author(s):  
K. H. Parekh ◽  
R. Milburn
Keyword(s):  
Failure Analysis ◽  
Failure Mechanisms ◽  
Photon Emission ◽  
Reliability Test ◽  
Input Output ◽  
End User ◽  
Final Test ◽  
Leakage Currents ◽  
Emission Microscopy ◽  
Scanning Electron

Abstract In the last several years emission microscopy has become an essential tool for failure analysis, specifically for VLSI devices. This paper describes various die related failure mechanisms in CMOS ASIC devices which were detected by emission microscopy. The failure analysis results discussed in this paper are primarily of the devices which were analyzed over the period of the last three years, 1994 - 1996. These devices were from a broad spectrum of final test failures, qualification and reliability test failures, special evaluation failures, testing and assembly failures at customer sites, and end user field failures. In addition to the failure mechanism statistic scanning electron micrographic illustrations of some of the failure mechanisms and associated damage are presented in this paper. The data presented in this paper clearly show the effectiveness of photon emission microscopy. The value of emission microscopy really lies in quick detection of failure locations on the die which failed functionally or due to excessive static IOD, functional IOD, or input/output leakage currents. It has certainly impacted tum around time of the analysis as significant reduction in analysis time has been achieved. In some cases same day turn around was possible.

Analysis of Delta Iddq Soft Fails on Pass Chips

2006 ◽  
Author(s):  
I. Österreicher ◽  
S. Eckl ◽  
B. Tippelt ◽  
S. Döring ◽  
R. Prang ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Failure Mode ◽  
Photon Emission ◽  
Complete Analysis ◽  
Functional Tests ◽  
Analysis Techniques ◽  
Atomic Force ◽  
Current Consumption ◽  
Emission Microscopy ◽  
Failure Localization

Abstract Depending on the field of application the ICs have to meet requirements that differ strongly from product to product, although they may be manufactured with similar technologies. In this paper a study of a failure mode is presented that occurs on chips which have passed all functional tests. Small differences in current consumption depending on the state of an applied pattern (delta Iddq measurement) are analyzed, although these differences are clearly within the usual specs. The challenge to apply the existing failure analysis techniques to these new fail modes is explained. The complete analysis flow from electrical test and Global Failure Localization to visualization is shown. The failure is localized by means of photon emission microscopy, further analyzed by Atomic Force Probing, and then visualized by SEM and TEM imaging.

Failure Analysis of Killer Defects and Yield Enhancement of Flat ROM Devices in Wafer Fabrication

2000 ◽  
Author(s):  
Y. N. Hua ◽  
Z. R. Guo ◽  
L. H. An ◽  
Shailesh Redkar
Keyword(s):  
Electron Microscope ◽  
Failure Analysis ◽  
Fault Isolation ◽  
Yield Enhancement ◽  
Wafer Fabrication ◽  
X Ray ◽  
Particle Contamination ◽  
Emission Microscopy ◽  
Microscopy Techniques ◽  
Scanning Electron

Abstract In this paper, some low yield cases in Flat ROM device (0.45 and 0.6 µm) were investigated. To find killer defects and particle contamination, KLA, bitmap and emission microscopy techniques were used in fault isolation. Reactive ion etching (RIE) and chemical delayering, 155 Wright Etch, BN+ Etch and scanning electron microscope (SEM) were used for identification and inspection of defects. In addition, energy-dispersive X-ray microanalysis (EDX) was used to determine the composition of the particle or contamination. During failure analysis, seven kinds of killer defects and three killer particles were found in Flat ROM devices. The possible root causes, mechanisms and elimination solutions of these killer defects/particles were also discussed.

Failure Analysis Methodology on Resistive Open Defects

2014 ◽  
Author(s):  
A.C.T. Quah ◽  
G.B. Ang ◽  
D. Nagalingam ◽  
C.Q. Chen ◽  
H.P. Ng ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Case Studies ◽  
Photon Emission ◽  
Analysis Methodology ◽  
Failure Path ◽  
Open Defect ◽  
Emission Microscopy ◽  
Open Defects ◽  
Logic Array ◽  
Failure Site

Abstract This paper describes the observation of photoemissions from saturated transistors along a connecting path with open defect in the logic array. By exploiting this characteristic phenomenon to distinguish open related issues, we described with 2 case studies using Photon Emission Microscopy, CAD navigation and layout tracing to identify the ‘open’ failure path. Further layout and EBAC analysis are then employed to effectively localize the failure site.

scholarly journals Reliability Study of Mechatronic Power Components Using Spectral Photon Emission Microscopy

2016 ◽  
Vol 5 (3) ◽  
pp. 20 ◽  
Author(s):  
N. Moultif ◽  
E. Joubert ◽  
O. Latry
Keyword(s):  
High Resolution ◽  
System Application ◽  
Diffraction Grating ◽  
Failure Mechanisms ◽  
Photon Emission ◽  
Emission Spectra ◽  
Power Devices ◽  
Reliability Study ◽  
Emission System ◽  
Emission Microscopy

In this paper, we present one of the most important failure analysis tools that permits the localizing and the identification of the failure mechanisms. It is a new spectral photon emission system, enabling to localize the failure, and quickly get the photon emission spectra that characterize the failure with high resolution. A diffraction grating is used as a spectrometer in the system. Application results on mechatronic power devices such as HEMT AlGaN/GAN and SiC MOSFETs are reported.

Failure Analysis of SOI Bipolar Device Using Photon Emission Microscopy

2004 ◽  
Author(s):  
Todd M. Simons ◽  
Bob Davis
Keyword(s):  
Failure Analysis ◽  
Failure Mechanism ◽  
Photon Emission ◽  
Silicon On Insulator ◽  
The Other ◽  
No Emission ◽  
Analysis Process ◽  
Soi Devices ◽  
Emission Microscopy ◽  
Optical Paths

Abstract Photon emission microscopy (PEM) provides a valuable first step in the failure analysis process. An analysis of a mixed signal bipolar/CMOS silicon on insulator (SOI) device revealed an abnormal emission site that appeared to emanate from the oxide isolation ring. Subsequent mechanical probing of the emitting bipolar transistor revealed node voltages nearly identical to a known good reference unit that had no emission site at the affected transistor. This article analyzes the reasons for the emission site on one transistor and not the other even though the node voltages were the same. It was observed that while the node voltages were nearly identical, the available current paths were not. The different paths directly related to the amount of available carriers for recombination in the base. The construction of the SOI device creates unique optical paths for emission sites not observed in non-SOI devices. It can be concluded that the failure mechanism does not always reside at the abnormal PEM site.

Failure Analysis of Sub-Micron Semiconductor Integrated Circuit Using Backside Photon Emission Microscopy

1999 ◽  
Author(s):  
Soon Lim ◽  
Jian Hua Bi ◽  
Lian Choo Goh ◽  
Soh Ping Neo ◽  
Sudhindra Tatti
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Integrated Circuit ◽  
Flip Chip ◽  
Photon Emission ◽  
Fault Isolation ◽  
Integrated Circuit Fabrication ◽  
Circuit Fabrication ◽  
Emission Microscopy ◽  
On Chip

Abstract The progress of modern day integrated circuit fabrication technology and packaging has made fault isolation using conventional emission microscopy via the top of the integrated circuit more difficult, if not impossible. This is primarily due to the use of increased levels and density of metal-interconnect, and the advent of new packaging technology, e.g. flip-chip, ball-grid array and lead-on-chip, etc. Backside photon emission microscopy, i.e. performing photon emission microscopy through the bulk of the silicon via the back of the integrated circuit is a solution to this problem. This paper outlines the failure analysis of sub-micron silicon integrated circuits using backside photon emission microscopy. Sample preparation, practical difficulties encountered and case histories will be discussed.

Silicon Dislocation Enhanced by Dynamic Voltage Stress

2007 ◽  
Author(s):  
Yu-Cheng Lin ◽  
Rock Chen ◽  
Sanan Liang ◽  
Scott Liao ◽  
Chorng Niou ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Silicon Substrate ◽  
Reliability Test ◽  
Final Test ◽  
Functional Failure ◽  
Root Cause ◽  
Voltage Stress ◽  
Dynamic Voltage ◽  
Lightly Doped Drain ◽  
The Relationship

Abstract In reliability test some chips suffered functional failure. Through a series of failure analysis experiments, the root cause was determined to be a silicon dislocation across LDD (Lightly Doped Drain) area causing p-n junction leakage. However, those failed samples all passed both CP (Chip Probe) and FT (Final Test) monitor. Therefore, it is reasonable to suspect that DVS (dynamic voltage stress) may enhance minor dislocations already existing before CP and FT. To prove this hypothesis, an experiment was designed to find the relationship between DVS and the depth of dislocation in silicon substrate. In conclusion, DVS could enhance dislocation across LDD area, which may induce reliability failure. Moreover, reliability concerns on this finding will be discussed in this paper.

scholarly journals Fault Isolation Approaches for Nanoscale TSV Interconnects in 3D Heterogenous Integration

2021 ◽  
Author(s):  
K.J.P. Jacobs ◽  
A. Jourdain ◽  
I. De Wolf ◽  
E. Beyne
Keyword(s):  
Photon Emission ◽  
Fault Isolation ◽  
Nanometer Scale ◽  
Induced Current ◽  
Contrast Imaging ◽  
Transmission Electron ◽  
Emission Microscopy ◽  
Open Defects ◽  
Voltage Contrast ◽  
Scanning Electron

Abstract We report optical and electron beam-based fault isolation approaches for short and open defects in nanometer scale through silicon via (TSV) interconnects (180×250 nm, 500 nm height). Short defects are localized by photon emission microscopy (PEM) and optical beam-induced current (OBIC) techniques, and open defects are isolated by active voltage contrast imaging in the scanning electron microscope (SEM). We confirm our results by transmission electron microscopy (TEM) based cross sectioning.

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