Gate Leakage Characterization and Fail Mode Analysis on 20 nm Technology Parametric Test Structures

Author(s):  
Satish Kodali ◽  
Wayne Zhao ◽  
Greg M. Johnson ◽  
Felix Beaudoin

Abstract Test structure characterization plays a predominant role throughout the entire development cycle of a product. They are used to understand the process windows and also help to monitor the health of line (HOL). One of the key principles in successfully monitoring the HOL is to establish passing and failing electrical criteria to various test structures. This paper shows electrical and physical characterization of one such test structure. Further, a novel way of establishing electrical signatures to specific defect fail mode finger prints for early identification and monitoring of process-related defects is proposed.

Author(s):  
Satish Kodali ◽  
Mia Nasimullah ◽  
Yuting Wei ◽  
Chong Khiam Oh ◽  
Felix Beaudoin

Abstract With increasing complexity involved in advance node semiconductor process development, dependability on parametric test structures has also increased significantly. Test structures play a predominant role throughout the entire development cycle of a product. It becomes very important to understand the root cause of failures at fastest pace to take necessary corrective actions. The use of ultra low K dielectrics for back end of line wafer build for advanced nodes created significant constraints on conventional beam imaging methods for fault isolation. This paper provides a streamlined process flow for root cause identification on shorts on advanced 20 nm and sub-20 nm technologies. Three unique cases are presented to demonstrate three typical situations identified in the process flow. They are blown capacitors, gate leakage, and resistance ladder short isolation.


2000 ◽  
Vol 147 (12) ◽  
pp. 4633 ◽  
Author(s):  
Joseph W. Tringe ◽  
Michael D. Deal ◽  
James D. Plummer

2013 ◽  
Vol 539 ◽  
pp. 178-183 ◽  
Author(s):  
Zheng Wu Jiang ◽  
Zi Long Deng ◽  
Nan Zhang

In this paper, pore structures and their changes of ordinary-strength concrete and high-strength concrete at different curing ages of 3, 28, 90 days were studied using thermoporometry, and the results were compared with those from MIP and NAD. The relationship between micro pores and porosity of concrete and its macroscopic properties was also studied. The results indicate that, compared to MIP, thermoporometry can characterize the features of pores with the diameter smaller than 100 nm in concrete accurately. The differences of macroscopic mechanical properties of concretes can be explained using the changes of their pore size distribution. After curing age of 28 days, the amount of pores with the diameter higher than 20 nm in high strength concrete changes little, but it decreases gradually in ordinary strength concrete. And pores with diameter smaller than 20 nm in concrete have little influence on the macroscopic mechanical property of concrete.


Author(s):  
X. Zhang ◽  
Y. Pan ◽  
T.T. Meek

Industrial microwave heating technology has emerged as a new ceramic processing technique. The unique advantages of fast sintering, high density, and improved materials properties makes it superior in certain respects to other processing methods. This work presents the structure characterization of a microwave sintered ceramic matrix composite.Commercial α-alumina powder A-16 (Alcoa) is chosen as the matrix material, β-silicon carbide whiskers (Third Millennium Technologies, Inc.) are used as the reinforcing element. The green samples consisted of 90 vol% Al2O3 powder and 10 vol% ultrasonically-dispersed SiC whiskers. The powder mixture is blended together, and then uniaxially pressed into a cylindrical pellet under a pressure of 230 MPa, which yields a 52% green density. The sintering experiments are carried out using an industry microwave system (Gober, Model S6F) which generates microwave radiation at 2.45 GHz with a maximum output power of 6 kW. The composites are sintered at two different temperatures (1550°C and 1650°C) with various isothermal processing time intervals ranging from 10 to 20 min.


Author(s):  
Martin Versen ◽  
Dorina Diaconescu ◽  
Jerome Touzel

Abstract The characterization of failure modes of DRAM is often straight forward if array related hard failures with specific addresses for localization are concerned. The paper presents a case study of a bitline oriented failure mode connected to a redundancy evaluation in the DRAM periphery. The failure mode analysis and fault modeling focus both on the root-cause and on the test aspects of the problem.


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