Process Flow Employed for Parametric Test Structure Shorts Fault Isolation in 20 nm and Sub-20 nm Technologies in High Throughput Foundries

2017 ◽  
Author(s):  
Satish Kodali ◽  
Mia Nasimullah ◽  
Yuting Wei ◽  
Chong Khiam Oh ◽  
Felix Beaudoin
Keyword(s):  
Process Development ◽  
Fault Isolation ◽  
Predominant Role ◽  
Process Flow ◽  
Parametric Test ◽  
Root Cause ◽  
Development Cycle ◽  
Root Cause Identification ◽  
20 Nm ◽  
Low K

Abstract With increasing complexity involved in advance node semiconductor process development, dependability on parametric test structures has also increased significantly. Test structures play a predominant role throughout the entire development cycle of a product. It becomes very important to understand the root cause of failures at fastest pace to take necessary corrective actions. The use of ultra low K dielectrics for back end of line wafer build for advanced nodes created significant constraints on conventional beam imaging methods for fault isolation. This paper provides a streamlined process flow for root cause identification on shorts on advanced 20 nm and sub-20 nm technologies. Three unique cases are presented to demonstrate three typical situations identified in the process flow. They are blown capacitors, gate leakage, and resistance ladder short isolation.

Process Flow Employed for Parametric Test Structure Chain Opens Fault Isolation in 20 nm and Sub-20 nm Technologies in High Throughput Foundries

2016 ◽  
Author(s):  
Satish Kodali ◽  
Yinzhe Ma ◽  
Chong Khiam Oh ◽  
Wayne Zhao ◽  
Felix Beaudoin
Keyword(s):  
Cross Sections ◽  
Process Development ◽  
Fault Isolation ◽  
Flow Sheet ◽  
Process Flow ◽  
Parametric Test ◽  
Root Cause ◽  
Voltage Contrast ◽  
Root Cause Identification ◽  
20 Nm

Abstract With increasing complexity involved in advance node semiconductor process development, dependability on parametric test structures has also increased significantly. Test structures play a predominant role throughout the entire development cycle of a product. They are used to understand the process windows and also help to monitor the health of a line. This work provides a process flow sheet for root cause identification on chain opens on advanced 20 nm and sub-20 nm technologies setting a standard guideline for a specific category fail type. It provides a consistent way of attack in a much more streamlined fashion. Further, dependability on TEM rather than convention FIB cross-sections provides shortest time to root cause identification. Three typical cases encountered are discussed to demonstrate the idea: embedded chain opens by electron beam absorbed current (EBAC) isolation, chains opens at level by EBAC isolation, and chains opens at level by passive voltage contrast isolation.

Gate Leakage Characterization and Fail Mode Analysis on 20 nm Technology Parametric Test Structures

2013 ◽  
Author(s):  
Satish Kodali ◽  
Wayne Zhao ◽  
Greg M. Johnson ◽  
Felix Beaudoin
Keyword(s):  
Early Identification ◽  
Test Structure ◽  
Structure Characterization ◽  
Physical Characterization ◽  
Mode Analysis ◽  
Predominant Role ◽  
Parametric Test ◽  
Development Cycle ◽  
20 Nm

Abstract Test structure characterization plays a predominant role throughout the entire development cycle of a product. They are used to understand the process windows and also help to monitor the health of line (HOL). One of the key principles in successfully monitoring the HOL is to establish passing and failing electrical criteria to various test structures. This paper shows electrical and physical characterization of one such test structure. Further, a novel way of establishing electrical signatures to specific defect fail mode finger prints for early identification and monitoring of process-related defects is proposed.

Precision Xe Plasma FIB Delayering for Physical Failure Analysis of Sub-20 nm Microprocessor Devices

2017 ◽  
Author(s):  
D. Zudhistira ◽  
V. Viswanathan ◽  
V. Narang ◽  
J.M. Chin ◽  
S. Sharang ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Dielectric Films ◽  
Planar Surface ◽  
Chemical Methods ◽  
Root Cause ◽  
Essential Step ◽  
Dielectric Layers ◽  
Wet Chemical ◽  
20 Nm ◽  
Low K

Abstract Deprocessing is an essential step in the physical failure analysis of ICs. Typically, this is accomplished by techniques such as wet chemical methods, RIE, and mechanical manual polishing. Manual polishing suffers from highly non-uniform delayering particularly for sub 20nm technologies due to aggressive back-end-of-line scaling and porous ultra low-k dielectric films. Recently gas assisted Xe plasma FIB has demonstrated uniform delayering of the metal and dielectric layers, achieving a planar surface of heterogeneous materials. In this paper, the successful application of this technique to delayer sub-20 nm microprocessor chips with real defects to root cause the failure is presented.

Unique Size-Dependent Challenges for BEOL Cleans in the Patterning of Sub-20 nm Features

2012 ◽  
Vol 195 ◽  
pp. 103-106 ◽  
Author(s):  
Kanwal Jit Singh
Keyword(s):  
Beam Theory ◽  
Dielectric Materials ◽  
Material Strength ◽  
K Value ◽  
Root Cause ◽  
Size Dependent ◽  
Performance Requirements ◽  
Black Boxes ◽  
20 Nm ◽  
Low K

BEOL Cleans has been and continues to be one of the most mysterious black boxes of semiconductor manufacturing. It has the unenviable task of removing post-plasma processing polymer residues, being compatible with ultra low-k dielectric materials that continue to scale k-value at the expense of material strength, and ensuring that any formulation that accomplishes the above objectives is also compatible with Cu and all other metals on the wafer used for liners or caps. In order to meet the performance requirements of next generation devices, Moore's law mandates continued scaling of dimensions with the additional challenges of size-dependent complexities for BEOL cleans development. Patterning of sub-20 nm features on thin ILD stacks suffers from the problems of etch-induced line undulation [1, 2] and cleans-induced pattern collapse [3]. High aspect ratio's, non-uniform drying, surface tension and low material strength have all been implicated as the root cause for pattern collapse during cleans [4]. Classical equations used to describe pattern collapse for resist lines that rely on 2D beam theory and finite element modeling [5] are not as applicable to patterned low-k dielectrics because material changes such as sidewall polymer residues, lowering of Young's modulus and changing pattern densities present different solid surfaces with widely varying wettability and diffusivity parameters [6, .

Fast Root Cause Identification Using Combination of Failure Analysis and In-Line Inspection

2017 ◽  
Author(s):  
Zhigang Song ◽  
Weihao Weng ◽  
Brett Engel
Keyword(s):  
Failure Analysis ◽  
Process Development ◽  
Second Step ◽  
Line Defect ◽  
Semiconductor Technology ◽  
Process Step ◽  
Root Cause ◽  
The Past ◽  
Root Cause Identification ◽  
The Relationship

Abstract Failure analysis plays an important role in yield improvement during semiconductor process development and device manufacturing. It includes two main steps. The first step is to find the defect and the second step is to identify the root cause. In the past, failure analysis mainly focused on the first step, namely how to find the defect for a failure; because in the previous generations of technology, once the defect was found, its root cause was relatively easy to be understood. As the current advanced semiconductor technology has become tremendously complicated, especially 3D devices, like FinFET, a defect found by failure analysis can be substantially transformed from its original defect by subsequent processes and can be totally different from its origin in size and shape. Thus, sometimes, the second step, identifying the root cause for a defect becomes more challenging and takes more time than the first step. With combination of failure analysis and inline inspection, it enables us to establish the relationship between the failure analysis defect and an in-line defect. This can link the defect for a device functional failure to its source layer and process step more quickly, leading to fast root cause identification. In this paper, the methodology was validated by fast identification of the root causes for three case studies in the latest FinFET technology.

Laser Voltage Probing in Failure Analysis of Advanced Integrated Circuits on SOI

2012 ◽  
Author(s):  
V.K. Ravikumar ◽  
R. Wampler ◽  
M.Y. Ho ◽  
J. Christensen ◽  
S.L. Phoa
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Case Studies ◽  
Timing Analysis ◽  
Fault Isolation ◽  
Root Cause ◽  
Root Cause Identification

Abstract Laser voltage probing is the newest generation of tools that perform timing analysis for electrical fault isolation in advanced failure analysis facilities. This paper uses failure analysis case studies on SOI to showcase the implementation of laser voltage probing in the failure analysis flow and highlight its significance in root-cause identification.

A New Failure Analysis Flow of Gate Oxide Integrity Failure in Wafer Fabrication

2009 ◽  
Author(s):  
Hua Younan ◽  
Chu Susan ◽  
Gui Dong ◽  
Mo Zhiqiang ◽  
Xing Zhenxiang ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Gate Dielectric ◽  
Dielectric Breakdown ◽  
Defect Density ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Fault Isolation ◽  
Wafer Fabrication ◽  
Root Cause ◽  
Gate Oxide Integrity

Abstract As device feature size continues to shrink, the reducing gate oxide thickness puts more stringent requirements on gate dielectric quality in terms of defect density and contamination concentration. As a result, analyzing gate oxide integrity and dielectric breakdown failures during wafer fabrication becomes more difficult. Using a traditional FA flow and methods some defects were observed after electrical fault isolation using emission microscopic tools such as EMMI and TIVA. Even with some success with conventional FA the root cause was unclear. In this paper, we will propose an analysis flow for GOI failures to improve FA’s success rate. In this new proposed flow both a chemical method, Wright Etch, and SIMS analysis techniques are employed to identify root cause of the GOI failures after EFA fault isolation. In general, the shape of the defect might provide information as to the root cause of the GOI failure, whether related to PID or contamination. However, Wright Etch results are inadequate to answer the questions of whether the failure is caused by contamination or not. If there is a contaminate another technique is required to determine what the contaminant is and where it comes from. If the failure is confirmed to be due to contamination, SIMS is used to further determine the contamination source at the ppm-ppb level. In this paper, a real case of GOI failure will be discussed and presented. Using the new failure analysis flow, the root cause was identified to be iron contamination introduced from a worn out part made of stainless steel.

Utilizing Nanoprobing and Circuit Diagnostics to Identify Key Failure Mechanism of Otherwise Nonvisible Defects in 20 nm Logic Devices

2014 ◽  
Author(s):  
M.K. Dawood ◽  
C. Chen ◽  
P.K. Tan ◽  
S. James ◽  
P.S. Limin ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Contact Layer ◽  
Fault Isolation ◽  
Tem Analysis ◽  
Logic Devices ◽  
Technology Advancement ◽  
Transmission Electron ◽  
Voltage Contrast ◽  
Almost All ◽  
20 Nm

Abstract In this work, we present two case studies on the utilization of advanced nanoprobing on 20nm logic devices at contact layer to identify the root cause of scan logic failures. In both cases, conventional failure analysis followed by inspection of passive voltage contrast (PVC) failed to identify any abnormality in the devices. Technology advancement makes identifying failure mechanisms increasingly more challenging using conventional methods of physical failure analysis (PFA). Almost all PFA cases for 20nm technology node devices and beyond require Transmission Electron Microscopy (TEM) analysis. Before TEM analysis can be performed, fault isolation is required to correctly determine the precise failing location. Isolated transistor probing was performed on the suspected logic NMOS and PMOS transistors to identify the failing transistors for TEM analysis. In this paper, nanoprobing was used to isolate the failing transistor of a logic cell. Nanoprobing revealed anomalies between the drain and bulk junction which was found to be due to contact gouging of different severities.

Analysis of Leakage Failures in Flash Memory Devices and Root Cause Identification

2000 ◽  
Author(s):  
J. N. C. de Luna ◽  
M. O. del Fierro ◽  
J. L. Muñoz
Keyword(s):  
Flash Memory ◽  
Electromagnetic Interference ◽  
Yield Loss ◽  
High Amplitude ◽  
Physical Analysis ◽  
Input Buffer ◽  
Automated Test Equipment ◽  
Root Cause ◽  
Root Cause Identification ◽  
Test Process

Abstract An advanced flash bootblock device was exceeding current leakage specifications on certain pins. Physical analysis showed pinholes on the gate oxide of the n-channel transistor at the input buffer circuit of the affected pins. The fallout contributed ~1% to factory yield loss and was suspected to be caused by electrostatic discharge or ESD somewhere in the assembly and test process. Root cause investigation narrowed down the source to a charged core picker inside the automated test equipment handlers. By using an electromagnetic interference (EMI) locator, we were able to observe in real-time the high amplitude electromagnetic pulse created by this ESD event. Installing air ionizers inside the testers solved the problem.

Root Cause Analysis Techniques Using Picosecond Time Resolved LADA

2014 ◽  
Author(s):  
Dan Bodoh ◽  
Kent Erington ◽  
Kris Dickson ◽  
George Lange ◽  
Carey Wu ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Picosecond Laser ◽  
Root Cause Analysis ◽  
Fault Isolation ◽  
Time Resolved ◽  
Cause Analysis ◽  
Root Cause ◽  
Design And Manufacturing ◽  
Multiple Interactions ◽  
Established Technique

Abstract Laser-assisted device alteration (LADA) is an established technique used to identify critical speed paths in integrated circuits. LADA can reveal the physical location of a speed path, but not the timing of the speed path. This paper describes the root cause analysis benefits of 1064nm time resolved LADA (TR-LADA) with a picosecond laser. It shows several examples of how picosecond TR-LADA has complemented the existing fault isolation toolset and has allowed for quicker resolution of design and manufacturing issues. The paper explains how TR-LADA increases the LADA localization resolution by eliminating the well interaction, provides the timing of the event detected by LADA, indicates the propagation direction of the critical signals detected by LADA, allows the analyst to infer the logic values of the critical signals, and separates multiple interactions occurring at the same site for better understanding of the critical signals.

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