Laser Voltage Imaging and Its Derivatives—Efficient Techniques to Address Defect on 28 nm Technology

Author(s):  
Thierry Parrassin ◽  
Guillaume Celi ◽  
Sylvain Dudit ◽  
Michel Vallet ◽  
Antoine Reverdy ◽  
...  

Abstract The Laser Voltage Imaging (LVI) technique, introduced in 2007 [1][2], has been demonstrated as a successful defect localization technique to address problems on advanced technologies. In this paper, several 28nm case studies are described on which the LVI technique and its derivatives provide a real added value to the defect localization part of the Failure Analysis flow. We will show that LVI images can be used as a great reference to improve the CAD alignment overlay accuracy which is critical for advanced technology debug. Then, we will introduce several case studies on 28nm technology on which Thermal Frequency Imaging (TFI) and Second Harmonic Detection (two LVI derivative techniques) allow efficient defect localization.

Author(s):  
Guillaume Celi ◽  
Sylvain Dudit ◽  
Thierry Parrassin ◽  
Michel Vallet ◽  
Philippe Perdu ◽  
...  

Abstract The Laser Voltage Imaging (LVI) technique [1], introduced in 2009, appears as a very promising approach for Failure Analysis application which allows mapping frequencies through the backside of integrated circuits. In this paper, we propose a new range of application based on the study of the LVI second harmonic for signal degradation analysis. After a theoretical study of the impact of signal degradation on the second harmonic, we will demonstrate the interest of this new approach on two case studies on ultimate technology (28nm). This technique is a new approach of failure analysis that maps timing degradation and duty cycle degradation. In order to confirm the degradations we will use the LVP Technique. The last part is two real case studies on which this LVI second harmonic technique was used to find the root cause of a 28nm process issue.


Author(s):  
Hui Peng Ng ◽  
Ghim Boon Ang ◽  
Chang Qing Chen ◽  
Alfred Quah ◽  
Angela Teo ◽  
...  

Abstract With the evolution of advanced process technology, failure analysis is becoming much more challenging and difficult particularly with an increase in more erratic defect types arising from non-visual failure mechanisms. Conventional FA techniques work well in failure analysis on defectively related issue. However, for soft defect localization such as S/D leakage or short due to design related, it may not be simple to identify it. AFP and its applications have been successfully engaged to overcome such shortcoming, In this paper, two case studies on systematic issues due to soft failures were discussed to illustrate the AFP critical role in current failure analysis field on these areas. In other words, these two case studies will demonstrate how Atomic Force Probing combined with Scanning Capacitance Microscopy were used to characterize failing transistors in non-volatile memory, identify possible failure mechanisms and enable device/ process engineers to make adjustment on process based on the electrical characterization result. [1]


Author(s):  
G. Ranganathan ◽  
V.K. Ravikumar ◽  
S.L. Phoa ◽  
C. Nemirow ◽  
N. Leslie

Abstract Laser Voltage imaging (LVI) is an established and widely used technique for isolating scan chain failures, especially those that are stuck-at a particular state. Enhancements such as second harmonic mapping have been beneficial in detecting a fault that is not stuck, but caused a shift in duty-cycle of the injected signal. In this paper, we describe Phase LVI which is constructed by integrating a lock-in amplifier as an enhancement to LVI for studying the relative phases between scan flops. Additionally we showcase case studies of successful fault isolation using phase LVI, where traditional LVI techniques were not successful.


Author(s):  
Sukho Lee ◽  
Marc van Veenhuizen ◽  
Paolo Navaretti ◽  
Gaia Donati

Abstract Lock-in techniques enable the detection of very small signals in a background that can be dominated by noise. This strength makes these techniques valuable especially for failure analysis of active devices where the deviation may be difficult to detect. This paper describes novel use case applications in which the lock-in amplifier plays a key role. The case studies covered are multi-frequency mapping fault isolation with nonperiodic patterns and frequency resonance measurement of a micro electro-mechanical system (MEMS) gyroscope. The paper presents how lock-in amplifiers enable digital failure analysis using compressed scan patterns. It reports on using a lock-in to characterize a MEMS gyroscope and on how to directly observe the gyroscope motion using phase laser voltage imaging/electro-optical frequency mapping. It can be concluded that the lock-in techniques form an essential part of the failure analysis toolkit and will only be more so with this study.


Author(s):  
Hui Peng Ng ◽  
Angela Teo ◽  
Ghim Boon Ang ◽  
Alfred Quah ◽  
N. Dayanand ◽  
...  

Abstract This paper discussed on how the importance of failure analysis to identify the root cause and mechanism that resulted in the MEMS failure. The defect seen was either directly on the MEMS caps or the CMOS integrated chip in wafer fabrication. Two case studies were highlighted in the discussion to demonstrate how the FA procedures that the analysts had adopted in order to narrow down to the defect site successfully on MEMS cap as well as on CMOS chip on MEMS package units. Besides the use of electrical fault isolation tool/technique such as TIVA for defect localization, a new physical deprocessing approach based on the cutting method was performed on the MEMS package unit in order to separate the MEMS from the Si Cap. This approach would definitely help to prevent the introduction of particles and artifacts during the PFA that could mislead the FA analyst into wrong data interpretation. Other FA tool such as SEM inspection to observe the physical defect and Auger analysis to identify the elements in the defect during the course of analysis were also documented in this paper.


Author(s):  
M.K. Dawood ◽  
T.H. Ng ◽  
P.K. Tan ◽  
H. Tan ◽  
S. James ◽  
...  

Abstract With further technology scaling, it becomes increasingly challenging for conventional methods of failure analysis (FA) to identify the cause of a failure. In this work, we present three case studies on the utilization of advanced nanoprobing for SRAM circuit analysis and fault identification on 20 nm technology node SRAM single bit devices. In the first 2 case studies, conventional failure analysis by passive voltage contrast (PVC) failed to identify any abnormality in the known failed bit. In the third case study, an abnormally bright PVC was observed by PVC inspection. In all three case studies, static noise margin of the SRAM bits during hold and read operations were performed to understand the circuit behavior of the failed bit cell. Next, nanoprobing on the individual transistors were performed to determine the failing transistor within the bit and the possible cause of the failure. TEM analysis was performed to identify and verify the failure mechanism.


Author(s):  
Srinath Rajaram ◽  
Rajesh Kabadi ◽  
Eric Barbian

Abstract Given the challenges FA Engineers have in fault localization, top-side analysis is facing a major challenge with today’s advanced packaging and shrinking of die sizes. At wafer and die level it is relatively easy to probe with little or no sample preparation. Greater challenges occur after the die is packaged. The difficulty further lies in non-destructively analyzing the die. Another issue with failure analysis is accurately deprocessing the device for probe pad deposition. Techniques like Electro Optical Probing (EOP) or Laser Voltage Probing (LVP) acquire electrical signals on transistors and create an activity map of the circuitry. In failure analysis, it is applied to localize defects. This paper discusses integrating EOP techniques in traditional FA to localize failure in mixed signal ICs. Three case studies were presented in this paper to establish the technique to be effective, quick and easy to probe non-invasively with minimal backside sample preparation.


Author(s):  
Jed Paolo Deligente ◽  
Saidaliah Sarip

Abstract Soft Defect Localization (SDL) method has been a common failure analysis technique used in fault isolation of temperature dependent failures, however proper signal conditioning and conversion of the monitored signal into a pass/fail signal are critical in acquiring an accurate defect location. This paper presents case studies where LabVIEW software using NI-PXI test platform was successfully implemented to effectively convert the failure mode into a pass/fail signal which provided a reliable SDL result.


2018 ◽  
Author(s):  
Ke-Ying Lin ◽  
Chih-Yi Tang ◽  
Yu Chi Wang

Abstract The paper demonstrates the moving of lock-in thermography (LIT) spot location by adjusting the lock-in frequency from low to high. Accurate defect localization in stacked-die devices was decided by the fixed LIT spot location after the lock-in frequency was higher than a specific value depending on the depth of the defect in the IC. Physical failure analysis was performed based on LIT results, which provided clear physical defect modes of the stacked-die devices.


Author(s):  
George M. Wenger ◽  
Richard J. Coyle ◽  
Patrick P. Solan ◽  
John K. Dorey ◽  
Courtney V. Dodd ◽  
...  

Abstract A common pad finish on area array (BGA or CSP) packages and printed wiring board (PWB) substrates is Ni/Au, using either electrolytic or electroless deposition processes. Although both Ni/Au processes provide flat, solderable surface finishes, there are an increasing number of applications of the electroless nickel/immersion gold (ENi/IAu) surface finish in response to requirements for increased density and electrical performance. This increasing usage continues despite mounting evidence that Ni/Au causes or contributes to catastrophic, brittle, interfacial solder joint fractures. These brittle, interfacial fractures occur early in service or can be generated under a variety of laboratory testing conditions including thermal cycling (premature failures), isothermal aging (high temperature storage), and mechanical testing. There are major initiatives by electronics industry consortia as well as research by individual companies to eliminate these fracture phenomena. Despite these efforts, interfacial fractures associated with Ni/Au surface finishes continue to be reported and specific failure mechanisms and root cause of these failures remains under investigation. Failure analysis techniques and methodologies are crucial to advancing the understanding of these phenomena. In this study, the scope of the fracture problem is illustrated using three failure analysis case studies of brittle interfacial fractures in area array solder interconnects. Two distinct failure modes are associated with Ni/Au surface finishes. In both modes, the fracture surfaces appear to be relatively flat with little evidence of plastic deformation. Detailed metallography, scanning electron microscopy (SEM), energy dispersive x-ray analysis (EDX), and an understanding of the metallurgy of the soldering reaction are required to avoid misinterpreting the failure modes.


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