Case Studies on Application of Electro Optical Probing (EOP) - A Noninvasive Backside Localization Technique in Failure Analysis

2019 ◽  
Author(s):  
Srinath Rajaram ◽  
Rajesh Kabadi ◽  
Eric Barbian
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
Case Studies ◽  
Fault Localization ◽  
Localization Technique ◽  
Localize Failure ◽  
Advanced Packaging ◽  
Optical Probing ◽  
Deposition Techniques ◽  
No Sample Preparation

Abstract Given the challenges FA Engineers have in fault localization, top-side analysis is facing a major challenge with today’s advanced packaging and shrinking of die sizes. At wafer and die level it is relatively easy to probe with little or no sample preparation. Greater challenges occur after the die is packaged. The difficulty further lies in non-destructively analyzing the die. Another issue with failure analysis is accurately deprocessing the device for probe pad deposition. Techniques like Electro Optical Probing (EOP) or Laser Voltage Probing (LVP) acquire electrical signals on transistors and create an activity map of the circuitry. In failure analysis, it is applied to localize defects. This paper discusses integrating EOP techniques in traditional FA to localize failure in mixed signal ICs. Three case studies were presented in this paper to establish the technique to be effective, quick and easy to probe non-invasively with minimal backside sample preparation.

Novel Failure Analysis Sample Preparation Techniques for PoP Packaging

2012 ◽  
Author(s):  
Ng Sea Chooi ◽  
Chor Theam Hock ◽  
Ma Choo Thye ◽  
Khoo Poh Tshin ◽  
Dan Bockelman
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
Failure Mechanisms ◽  
Preparation Process ◽  
Space Saving ◽  
Optical Probing ◽  
Preparation Techniques

Abstract Trends in the packaging of semiconductors are towards miniaturization and high functionality. The package-on-package(PoP) with increasing demands is beneficial in cost and space saving. The main failure mechanisms associated with PoP technology, including open joints and warpage, have created a lot of challenges for Assembly and Failure Analysis (FA). This paper outlines the sample preparation process steps to overcome the challenges to enable successful failure analysis and optical probing.

Advanced Acoustic Micro Imaging Applications: Deciphering Multiple Acoustic Echoes and Reflections

2004 ◽  
Author(s):  
Andrew J. Komrowski ◽  
Luis A. Curiel ◽  
Daniel J. D. Sullivan ◽  
Quang Nguyen ◽  
Lisa Logan-Willams
Keyword(s):  
Failure Analysis ◽  
Case Studies ◽  
New Technologies ◽  
Electronic Packages ◽  
Advanced Packaging ◽  
Ic Package ◽  
Non Destructive

Abstract The acquisition of reliable Acoustic Micro Images (AMI) are an essential non-destructive step in the Failure Analysis (FA) of electronic packages. Advanced packaging and new IC materials present challenges to the collection of reliable AMI signals. The AMI is complicated due to new technologies that utilize an increasing number of interfaces in ICs and packages. We present two case studies in which it is necessary to decipher the acoustic echoes from the signals generated by the interface of interest in order to acquire trustworthy information about the IC package.

A Sample Preparation on Decapsulation Methodology for Effective Failure Analysis on Thin Small Leadless (TSLP) Flip Chip Package with Copper Pillar (CuP) Bump Interconnect Technology

2014 ◽  
Author(s):  
Gwee Hoon Yen ◽  
Ng Kiong Kay
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
Flip Chip ◽  
Fault Localization ◽  
Cost Effective ◽  
Fault Isolation ◽  
Voltage Contrast ◽  
Interconnect Technology

Abstract Today, failure analysis involving flip chip [1] with copper pillar bump packaging technologies would be the major challenges faced by analysts. Most often, handling on the chips after destructive chemical decapsulation is extremely critical as there are several failure analysis steps to be continued such as chip level fault localization, chip micro probing for fault isolation, parallel lapping [2, 3, 4] and passive voltage contrast. Therefore, quality of sample preparation is critical. This paper discussed and demonstrated a quick, reliable and cost effective methodology to decapsulate the thin small leadless (TSLP) flip chip package with copper pillar (CuP) bump interconnect technology.

Impacts of Sample Preparation Methodology on TEM Failure Analysis of Advanced Semiconductor Devices

2011 ◽  
Author(s):  
Yongkai Zhou ◽  
Jie Zhu ◽  
Han Wei Teo ◽  
ACT Quah ◽  
Lei Zhu ◽  
...  
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
Case Studies ◽  
Thickness Measurement ◽  
Interface Roughness ◽  
Silicide Formation ◽  
Cross Sectional ◽  
Inspection Method ◽  
Low Mass

Abstract In this paper, two failure analysis case studies are presented to demonstrate the importance of sample preparation procedures to successful failure analyses. Case study 1 establishes that Palladium (Pd) cannot be used as pre-FIB coating for SiO2 thickness measurement due to the spontaneously Pd silicide formation at the SiO2/Si interface. Platinum (Pt) is thus recommended, in spite of the Pt/SiO2 interface roughness, as the pre-FIB coating in this application. In the second case study, the dual-directional TEM inspection method is applied to characterize the profile of the “invisible” tungsten residue defect. The tungsten residue appears invisible in the planeview specimen due to the low mass-thickness contrast. It is then revealed in the cross-sectional TEM inspection.

Lock-in Thermography for Flip-Chip Package Failure Analysis

2012 ◽  
Author(s):  
Lihong Cao ◽  
Manasa Venkata ◽  
Jeffery Huynh ◽  
Joseph Tan ◽  
Meng-Yeow Tay ◽  
...  
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
Case Studies ◽  
Flip Chip ◽  
Organic Substrate ◽  
Fault Isolation ◽  
Lock In

Abstract This paper describes the application of lock-in thermography (LIT) for flip-chip package-level failure analysis. LIT successfully detected and localized short failures related to both die/C4 bumps and package defects inside the organic substrate. The detail sample preparation to create short defects at different layers, LIT fault isolation methodology, and case studies performed with LIT are also presented in this paper.

Case Study—Lock-in Thermography Application in Failure Analysis of a System Level DC-DC μModule Regulator

2017 ◽  
Author(s):  
Vikash Kumar ◽  
Devraj Karthikeyan
Keyword(s):  
Heat Source ◽  
Failure Analysis ◽  
Case Studies ◽  
Fault Localization ◽  
System Level ◽  
Thermal Failure ◽  
Analysis Process ◽  
Lock In

Abstract Fault localization is a common failure analysis process that is used to detect the anomaly on a faulty device. The Infrared Lock-In Thermography (LIT) is one of the localization techniques which can be used on the packaged chips for identifying the heat source which is a result of active damage. This paper extends the idea that the LIT analysis for fault localization is not only limited to the devices within the silicon die but it also highlights thermal failure indications of other components on the PCB (like capacitors, FETs etc on a system level DC-DC μmodule). The case studies presented demonstrate the effectiveness of using LIT in the Failure analysis process of a system level DC-DC μmodule regulator

Use of 3D X-Ray Microscopy for BEOL and Advanced Packaging Failure Analysis

2017 ◽  
Author(s):  
Christian Schmidt ◽  
Stephen T. Kelly ◽  
Ingrid De Wolf
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
Fault Isolation ◽  
Short Introduction ◽  
Basic Principles ◽  
X Ray ◽  
Line Feature ◽  
Advanced Packaging ◽  
New Challenges ◽  
Semiconductor Packages

Abstract With the growing complexity and interconnect density of modern semiconductor packages, package level FA is also facing new challenges and requirements. 3D X-Ray Microscopy (XRM) is considered a key method to fulfill these requirements and enable high success FA yield. After a short introduction into the basic principles of lab-based X-Ray tomography, 2 different approaches of X-Ray investigations are discussed and an integration into the daily FA flow is proposed. In the first example, fault isolation on a fully packaged device is demonstrated using a stacked die device. In the second example, a newly developed sample preparation flow in combination with Nanoscale 3D X-Ray Microscopy for Chip-Package-Interaction and Back-end-of-line feature imaging is introduced.

Laser Voltage Imaging and Its Derivatives—Efficient Techniques to Address Defect on 28 nm Technology

2013 ◽  
Author(s):  
Thierry Parrassin ◽  
Guillaume Celi ◽  
Sylvain Dudit ◽  
Michel Vallet ◽  
Antoine Reverdy ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Case Studies ◽  
Second Harmonic ◽  
Advanced Technology ◽  
Added Value ◽  
Harmonic Detection ◽  
Localization Technique ◽  
Voltage Imaging ◽  
Advanced Technologies ◽  
Defect Localization

Abstract The Laser Voltage Imaging (LVI) technique, introduced in 2007 [1][2], has been demonstrated as a successful defect localization technique to address problems on advanced technologies. In this paper, several 28nm case studies are described on which the LVI technique and its derivatives provide a real added value to the defect localization part of the Failure Analysis flow. We will show that LVI images can be used as a great reference to improve the CAD alignment overlay accuracy which is critical for advanced technology debug. Then, we will introduce several case studies on 28nm technology on which Thermal Frequency Imaging (TFI) and Second Harmonic Detection (two LVI derivative techniques) allow efficient defect localization.

A Sample Preparation Methodology for Effective Failure Analysis of Trench Power MOSFET

2013 ◽  
Author(s):  
Yan Li ◽  
S.K. Loh ◽  
C.Q. Chen ◽  
G.B. Ang ◽  
A.C.T. Quah ◽  
...  
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
Success Rate ◽  
Defect Detection ◽  
Fault Localization ◽  
Power Mosfet

Abstract This paper describes a sample preparation methodology for Trench Power MOSFET that significantly improved our failure analysis success rate for trench bottom defect. With precise fault localization and subsequent a unique physical failure analysis using parallel polishing method on Trench Power MOSFET, This enabled defect detection from the trench top to the trench bottom.

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