Characterization and Simulation of a Body Biased Structure in Triple-Well Technology under Pulsed Photoelectric Laser Stimulation

2014 ◽  
Author(s):  
N. Borrel ◽  
C. Champeix ◽  
M. Lisart ◽  
A. Sarafianos ◽  
E. Kussener ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Integrated Circuit ◽  
Laser Power ◽  
Pulsed Laser ◽  
Electrical Model ◽  
Activation Threshold ◽  
Laser Stimulation ◽  
Laser Illumination ◽  
High Laser ◽  
Complex Circuits

Abstract This study is driven by the need to optimize failure analysis methodologies based on laser/silicon interactions inside an integrated circuit using a triple-well process. It is therefore mandatory to understand the behavior of elementary devices to laser illumination, in order to model and predict the behavior of more complex circuits. This paper presents measurements of the photoelectric currents induced by a pulsed laser on a triple-well Psubstrate/DeepNwell/Pwell structure dedicated to low power body biasing techniques. It reveals possible bipolar transistor activation at high laser power. This activation threshold revealed its dependence on laser power and wells biasing. Based on the measurements made during our experiments, an electrical model is proposed that makes it possible to simulate the effects induced by photoelectric laser stimulation.

scholarly journals Characterization and TCAD Simulation of 90nm Technology PMOS Transistor under Continuous Photoelectric Laser Stimulation for Failure Analysis Improvement

2012 ◽  
Author(s):  
R. Llido ◽  
A. Sarafianos ◽  
O. Gagliano ◽  
V. Serradeil ◽  
V. Goubier ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Integrated Circuit ◽  
Computer Aided Design ◽  
Laser Stimulation ◽  
Modeling Technology ◽  
Physical Simulations ◽  
Complex Circuits ◽  
Aided Design ◽  
Long Channel ◽  
Pmos Transistor

Abstract This study responds to our need to optimize failure analysis methodologies based on laser/silicon interactions, using the functional response of an integrated circuit to local laser stimulation. Thus it is mandatory to understand the behavior of elementary devices under laser stimulation, in order to model and anticipate the behavior of more complex circuits. This paper characterizes and analyses effects induced by a static photoelectric laser on a 90 nm technology PMOS transistor. Comparisons between currents induced in short or long channel transistors for both ON and OFF states are made. Experimental measurements are correlated to Finite Elements Modeling Technology Computer Aided Design (TCAD) analyses. These physical simulations give a physical insight of carriers generation and charge transport phenomena in the devices.

Scanning Optical Microscopy Application in Micron® Memory Devices

2005 ◽  
Author(s):  
Wong Yaw Yuan ◽  
T.L. Edmund Poh ◽  
David Lam
Keyword(s):  
Failure Analysis ◽  
Integrated Circuit ◽  
Semiconductor Industry ◽  
Fault Isolation ◽  
Memory Devices ◽  
Back Side ◽  
Induced Voltage ◽  
Scanning Optical Microscopy ◽  
Side Emission ◽  
Complex Circuits

Abstract The migration to smaller geometries has translated to an increase in the number of transistors possible in each integrated circuit. Failure analysis of such complex circuits presents a major challenge to the semiconductor industry and is a driving force behind the considerable interest in nondestructive, cost-efficient, “shortcut” fault isolation techniques. In this paper, we present the application of thermal-induced voltage alteration (TIVA) for failure analysis of 0.11µm technology memory devices and demonstrate the key aspects of this technique. The back side TIVA results are compared with analysis performed using back side emission microscopy (EMMI), and the limitations of EMMI are highlighted. The advantages and limitations of the TIVA technique are also discussed.

Pulsed Laser Polymerization of Alkyl Acrylates: Potential Effects of the Oxygen Presence and High Laser Power

2006 ◽  
Vol 207 (1) ◽  
pp. 81-89 ◽  
Author(s):  
Patrice Castignolles ◽  
Anatoly N. Nikitin ◽  
Laurence Couvreur ◽  
Guillaume Mouraret ◽  
Bernadette Charleux ◽  
...  
Keyword(s):  
Laser Power ◽  
Pulsed Laser ◽  
Alkyl Acrylates ◽  
High Laser Power ◽  
High Laser ◽  
Pulsed Laser Polymerization

Timing Characterization of a Tester Operated Integrated Circuit by Continuous and Pulsed Laser Stimulation

2010 ◽  
Author(s):  
Tuba Kiyan ◽  
Christof Brillert ◽  
Christian Boit
Keyword(s):  
Integrated Circuit ◽  
Continuous Wave ◽  
Supply Voltage ◽  
Pulsed Laser ◽  
Drain Current ◽  
Propagation Delay ◽  
Laser Stimulation ◽  
Laser Condition ◽  
Secondary Phenomenon

Abstract The scope of this work is to investigate the timing characteristics of a state of the art fully functional IC through continuous wave (CW) and pulsed laser stimulation. The propagation delay of a gate depends on the drain current of nMOS and pMOS transistors, load capacitance and supply voltage. Localized photocurrent induced by laser beam alters some of these electrical characteristics, resulting in a change in the switching time of the gate. In addition to the desired local timing influence, a global effect on the timing throughout the full scanning period occurs as secondary phenomenon that - if not taken into account properly, may mask the local signal. This effect is strong under CW laser operation and can be drastically reduced in pulsed laser condition.

Failure Analysis of CDM-ESD Damage in a GaAs RFIC

2000 ◽  
Author(s):  
Amy Poe ◽  
Steve Brockett ◽  
Tony Rubalcava
Keyword(s):  
Radio Frequency ◽  
Failure Analysis ◽  
Integrated Circuit ◽  
Production Test ◽  
Analysis Techniques ◽  
Device Model ◽  
Charged Device ◽  
Subsequent Failure

Abstract The intent of this work is to demonstrate the importance of charged device model (CDM) ESD testing and characterization by presenting a case study of a situation in which CDM testing proved invaluable in establishing the reliability of a GaAs radio frequency integrated circuit (RFIC). The problem originated when a sample of passing devices was retested to the final production test. Nine of the 200 sampled devices failed the retest, thus placing the reliability of all of the devices in question. The subsequent failure analysis indicated that the devices failed due to a short on one of two capacitors, bringing into question the reliability of the dielectric. Previous ESD characterization of the part had shown that a certain resistor was likely to fail at thresholds well below the level at which any capacitors were damaged. This paper will discuss the failure analysis techniques which were used and the testing performed to verify the failures were actually due to ESD, and not caused by weak capacitors.

Application of Fast Laser Deprocessing Techniques in Physical Failure Analysis on SRAM Memory of Advance Technology

2014 ◽  
Author(s):  
H.H. Yap ◽  
P.K. Tan ◽  
G.R. Low ◽  
M.K. Dawood ◽  
H. Feng ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Integrated Circuit ◽  
Cost Effective ◽  
Tetraethyl Orthosilicate ◽  
Ic Design ◽  
Advance Technology ◽  
Defect Identification ◽  
Technology Scaling ◽  
And Function ◽  
Metal Layers

Abstract With technology scaling of semiconductor devices and further growth of the integrated circuit (IC) design and function complexity, it is necessary to increase the number of transistors in IC’s chip, layer stacks, and process steps. The last few metal layers of Back End Of Line (BEOL) are usually very thick metal lines (>4μm thickness) and protected with hard Silicon Dioxide (SiO2) material that is formed from (TetraEthyl OrthoSilicate) TEOS as Inter-Metal Dielectric (IMD). In order to perform physical failure analysis (PFA) on the logic or memory, the top thick metal layers must be removed. It is time-consuming to deprocess those thick metal and IMD layers using conventional PFA workflows. In this paper, the Fast Laser Deprocessing Technique (FLDT) is proposed to remove the BEOL thick and stubborn metal layers for memory PFA. The proposed FLDT is a cost-effective and quick way to deprocess a sample for defect identification in PFA.

In-Line Defect to Bitmap Signature Correlation: A Shortcut to Physical FA Results

2000 ◽  
Author(s):  
Julie Segal ◽  
Arman Sagatelian ◽  
Bob Hodgkins ◽  
Tom Ho ◽  
Ben Chu ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Integrated Circuit ◽  
Failure Mechanisms ◽  
Memory Devices ◽  
Line Defect ◽  
Yield Improvement ◽  
Electrical Test ◽  
Large Numbers ◽  
Improvement Process ◽  
Existing Data

Abstract Physical failure analysis (FA) of integrated circuit devices that fail electrical test is an important part of the yield improvement process. This article describes how the analysis of existing data from arrayed devices can be used to replace physical FA of some electrical test failures, and increase the value of physical FA results. The discussion is limited to pre-repair results. The key is to use classified bitmaps and determine which signature classification correlates to which type of in-line defect. Using this technique, physical failure mechanisms can be determined for large numbers of failures on a scale that would be unfeasible with de-processing and physical FA. If the bitmaps are classified, two-way correlation can be performed: in-line defect to bitmap failure, as well as bitmap signature to in-line defect. Results also demonstrate the value of analyzing memory devices failures, even those that can be repaired, to gain understanding of defect mechanisms.

Picosecond Single-Photon and Femtosecond Two-Photon Pulsed Laser Stimulation for IC Characterization and Failure Analysis

2009 ◽  
Author(s):  
V. Pouget ◽  
E. Faraud ◽  
K. Shao ◽  
S. Jonathas ◽  
D. Horain ◽  
...  
Keyword(s):  
Femtosecond Laser ◽  
Single Photon ◽  
Pulsed Laser ◽  
Laser Pulses ◽  
Femtosecond Laser Pulses ◽  
Ultrashort Laser Pulses ◽  
Laser Stimulation ◽  
Two Photon ◽  
Resolution Improvement ◽  
Ultrashort Laser

Abstract This paper presents the use of pulsed laser stimulation with picosecond and femtosecond laser pulses. We first discuss the resolution improvement that can be expected when using ultrashort laser pulses. Two case studies are then presented to illustrate the possibilities of the pulsed laser photoelectric stimulation in picosecond single-photon and femtosecond two-photon modes.

Dual Port RAM MBIST Failure Analysis Using Time Resolved Dynamic Laser Stimulation

2008 ◽  
Author(s):  
Jonathan Shaw ◽  
Christopher McMahon ◽  
Yin Shyang Ng ◽  
Félix Beaudoi
Keyword(s):  
Failure Analysis ◽  
Embedded Memory ◽  
Complementary Information ◽  
Time Resolved ◽  
Laser Stimulation ◽  
Specific Indication ◽  
Read Operation ◽  
Site Localization

Abstract This paper presents the use of Dynamic Laser Stimulation (DLS) and Time-Resolved DLS (TR-DLS) to provide fail site localization and complementary information on a failed embedded memory IC. In this study, an embedded dual port RAM within a 90nm IC that failed one of the Memory Built-In Self Tests (MBISTs) was investigated. This technique rapidly localized the failing area within the memory read/write circuitry. The TR-DLS provided maps for each operation of the MBIST pattern. With this information, the failure was clearly identified as a read operation failure. The TR-DLS technique also provided much refined site signature (down to just one net) within the sense amp of the Port B of the dual port RAM. This information provided very specific indication on how to improve the operation of that particular sense amp circuitry within the dual port RAM Memory.

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