Timing Characterization of a Tester Operated Integrated Circuit by Continuous and Pulsed Laser Stimulation

2010 ◽  
Author(s):  
Tuba Kiyan ◽  
Christof Brillert ◽  
Christian Boit
Keyword(s):  
Integrated Circuit ◽  
Continuous Wave ◽  
Supply Voltage ◽  
Pulsed Laser ◽  
Drain Current ◽  
Propagation Delay ◽  
Laser Stimulation ◽  
Laser Condition ◽  
Secondary Phenomenon

Abstract The scope of this work is to investigate the timing characteristics of a state of the art fully functional IC through continuous wave (CW) and pulsed laser stimulation. The propagation delay of a gate depends on the drain current of nMOS and pMOS transistors, load capacitance and supply voltage. Localized photocurrent induced by laser beam alters some of these electrical characteristics, resulting in a change in the switching time of the gate. In addition to the desired local timing influence, a global effect on the timing throughout the full scanning period occurs as secondary phenomenon that - if not taken into account properly, may mask the local signal. This effect is strong under CW laser operation and can be drastically reduced in pulsed laser condition.

scholarly journals A high efficiency 10W MMIC PA for K-b and satellite communications

2021 ◽  
pp. 1-13
Author(s):  
Paolo Colantonio ◽  
Rocco Giofrè ◽  
Fabio Vitobello ◽  
Mariano Lòpez ◽  
Lorena Cabrìa
Keyword(s):  
Integrated Circuit ◽  
High Efficiency ◽  
Continuous Wave ◽  
Satellite Communications ◽  
Operating Conditions ◽  
Junction Temperature ◽  
Worst Case ◽  
Power Added Efficiency ◽  
Operating Bandwidth

Abstract This paper discusses the design steps and experimental characterization of a monolithic microwave integrated circuit (MMIC) power amplifier developed for the next generation of K-band 17.3–20.2 GHz very high throughput satellites. The technology used is a commercially available 100-nm gate length gallium nitride on silicon process. The chip was developed taking into account the demanding constraints of the spacecraft and, in particular, carefully considering the thermal constraints of such technology, in order to keep the junction temperature in all devices below 160°C in the worst-case condition (i.e., maximum environmental temperature of 85°C). The realized MMIC, based on a three-stage architecture, was first characterized on-wafer in pulsed regime and, subsequently, mounted in a test-jig and characterized under continuous wave operating conditions. In 17.3–20.2 GHz operating bandwidth, the built amplifier provides an output power >40 dBm with a power added efficiency close to 30% (peak >40%) and 22 dB of power gain.

Characterization and Simulation of a Body Biased Structure in Triple-Well Technology under Pulsed Photoelectric Laser Stimulation

2014 ◽  
Author(s):  
N. Borrel ◽  
C. Champeix ◽  
M. Lisart ◽  
A. Sarafianos ◽  
E. Kussener ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Integrated Circuit ◽  
Laser Power ◽  
Pulsed Laser ◽  
Electrical Model ◽  
Activation Threshold ◽  
Laser Stimulation ◽  
Laser Illumination ◽  
High Laser ◽  
Complex Circuits

Abstract This study is driven by the need to optimize failure analysis methodologies based on laser/silicon interactions inside an integrated circuit using a triple-well process. It is therefore mandatory to understand the behavior of elementary devices to laser illumination, in order to model and predict the behavior of more complex circuits. This paper presents measurements of the photoelectric currents induced by a pulsed laser on a triple-well Psubstrate/DeepNwell/Pwell structure dedicated to low power body biasing techniques. It reveals possible bipolar transistor activation at high laser power. This activation threshold revealed its dependence on laser power and wells biasing. Based on the measurements made during our experiments, an electrical model is proposed that makes it possible to simulate the effects induced by photoelectric laser stimulation.

Fabrication Process, Application and Future for An Elemental Level Vertically Integratedcircuit (Elvic)

1985 ◽  
Vol 53 ◽  
Author(s):  
Tadayoshi Enomoto
Keyword(s):  
Integrated Circuit ◽  
Supply Voltage ◽  
Lower Layer ◽  
Propagation Delay ◽  
Fabrication Process ◽  
Ring Oscillator ◽  
Thermal Compression ◽  
Face To Face ◽  
Integration Density ◽  
High Production

ABSTRACTA new double-layered stacked LSI fabrication process has been developed for the purpose of realizing short fabrication turn-around time, high fabrication yield and high integration density. This process, which is named “Elemental Level Vertical Integrated Circuit (ELVIC)” technology, puts 2 convenfionally made LSI chips face to face andbonds them by thermal compression. The process includes, in addition to the conventionalLSI fabrication process, vertical interconnection (VI) formation in the upper and lower LSI layers, planarization of both upper and lower layer surfaces, and inter-level connections using pressure and heat. In the experimental version, about 52,000 10 x 10 μm2 Au-on-Ti VIs were connected on a 5 x 5 mm2 chip. Each pair of mated VIs is measured for tensile strength of 4 mg force. A 2-layer, 31-stage inter- CMOS/bulk ring oscillator consisting of p-channel MOSFETs on the upppr layerand nchannel MOSFETs on the lower layer has been built. Propagation delay time per stageis 1.86 nsec at the supply voltage of 5 V. ELVIC technology can produce a variety of benefits such as high production yield, doubling integration density, latch-up free CMOS LSIs, radiation damage free LSls, multi-function, and complete mixing of bipolar, CMOS andGaAs technologies.

Fabrication process, experimental results, and application for an elemental level vertically intergrated circuit (ELVIC)

1986 ◽  
Vol 1 (4) ◽  
pp. 552-559 ◽  
Author(s):  
Tadayoshi Enomoto
Keyword(s):  
Integrated Circuit ◽  
Supply Voltage ◽  
Lower Layer ◽  
Propagation Delay ◽  
Fabrication Process ◽  
Ring Oscillator ◽  
Thermal Compression ◽  
Face To Face ◽  
Integration Density ◽  
Intergrated Circuit

A new double-layered stacked LSI fabrication process has been developed for the purpose of realizing short fabrication turn-around time, high fabrication yield, and high integration density. This process, which is named “Elemental Level Vertical Integrated Circuit (ELVIC)” technology, puts two conventionally made LSI chips face to face and bonds them by thermal compression. The process includes, in addition to the conventional LSI fabrication process, vertical interconnection (VI) formation in the upper and lower LSI layers, planarization of both upper and lower layer surfaces, and inter-level connections using pressure and heat. In the experimental version, about 52 000 10X10μm2 Au-on-Ti VIs were connected on a 5×5 mm2 chip. Each pair of mated VIs was measured and had a tensile strength of 4 mg · force. A two-layer, 31-stage inter-CMOS/bulk ring oscillator consisting of p-channel MOSFETs on the upper layer and n-channel MOSFETs on the lower layer has been built. Propagation delay time per stage is 1.86 ns at the supply voltage of 5 V. ELVIC technology can produce a variety of benefits such as high production yield, doubling integration density, latchup-free CMOS LSIs, radiation-damage-free LSIs, multifunction, and complete mixing of bipolar, CMOS, and GaAs technologies.

Characterization of RF Sputtered ZnO Piezoelectric Films Using Transmission Electron Microscope

1975 ◽  
Vol 33 ◽  
pp. 86-87
Author(s):  
Kemining W. Yeh ◽  
Richard S. Muller ◽  
Wei-Kuo Wu ◽  
Jack Washburn
Keyword(s):  
Integrated Circuit ◽  
Acoustic Waves ◽  
New Technology ◽  
Surface Acoustic Waves ◽  
Electromechanical Properties ◽  
Leading Role ◽  
Saw Devices ◽  
Transmission Electron ◽  
High Degree

Considerable and continuing interest has been shown in the thin film transducer fabrication for surface acoustic waves (SAW) in the past few years. Due to the high degree of miniaturization, compatibility with silicon integrated circuit technology, simplicity and ease of design, this new technology has played an important role in the design of new devices for communications and signal processing. Among the commonly used piezoelectric thin films, ZnO generally yields superior electromechanical properties and is expected to play a leading role in the development of SAW devices.

Failure Analysis of CDM-ESD Damage in a GaAs RFIC

2000 ◽  
Author(s):  
Amy Poe ◽  
Steve Brockett ◽  
Tony Rubalcava
Keyword(s):  
Radio Frequency ◽  
Failure Analysis ◽  
Integrated Circuit ◽  
Production Test ◽  
Analysis Techniques ◽  
Device Model ◽  
Charged Device ◽  
Subsequent Failure

Abstract The intent of this work is to demonstrate the importance of charged device model (CDM) ESD testing and characterization by presenting a case study of a situation in which CDM testing proved invaluable in establishing the reliability of a GaAs radio frequency integrated circuit (RFIC). The problem originated when a sample of passing devices was retested to the final production test. Nine of the 200 sampled devices failed the retest, thus placing the reliability of all of the devices in question. The subsequent failure analysis indicated that the devices failed due to a short on one of two capacitors, bringing into question the reliability of the dielectric. Previous ESD characterization of the part had shown that a certain resistor was likely to fail at thresholds well below the level at which any capacitors were damaged. This paper will discuss the failure analysis techniques which were used and the testing performed to verify the failures were actually due to ESD, and not caused by weak capacitors.

Picosecond Single-Photon and Femtosecond Two-Photon Pulsed Laser Stimulation for IC Characterization and Failure Analysis

2009 ◽  
Author(s):  
V. Pouget ◽  
E. Faraud ◽  
K. Shao ◽  
S. Jonathas ◽  
D. Horain ◽  
...  
Keyword(s):  
Femtosecond Laser ◽  
Single Photon ◽  
Pulsed Laser ◽  
Laser Pulses ◽  
Femtosecond Laser Pulses ◽  
Ultrashort Laser Pulses ◽  
Laser Stimulation ◽  
Two Photon ◽  
Resolution Improvement ◽  
Ultrashort Laser

Abstract This paper presents the use of pulsed laser stimulation with picosecond and femtosecond laser pulses. We first discuss the resolution improvement that can be expected when using ultrashort laser pulses. Two case studies are then presented to illustrate the possibilities of the pulsed laser photoelectric stimulation in picosecond single-photon and femtosecond two-photon modes.

Timing Sensitivity Analysis of Logical Nodes in Scan Design Integrated Circuits by Pulsed Diode Laser Stimulation

2008 ◽  
Author(s):  
T. Kiyan ◽  
C. Boit ◽  
C. Brillert
Keyword(s):  
Laser Pulse ◽  
Integrated Circuits ◽  
Continuous Wave ◽  
Fault Injection ◽  
Scan Design ◽  
Flip Flop ◽  
Laser Stimulation ◽  
Scan Chain ◽  
P Type ◽  
Scan Pattern

Abstract In this paper, a methodology based upon laser stimulation and a comparison of continuous wave and pulsed laser operation will be presented that localizes the fault relevant sites in a fully functional scan chain cell. The technique uses a laser incident from the backside to inject soft faults into internal nodes of a master-slave scan flip-flop in consequence of localized photocurrent. Depending on the illuminated type of the transistors (n- or p-type), injection of a logic ‘0’ or ‘1’ into the master or the slave stage of a flip-flop takes place. The laser pulse is externally triggered and can easily be shifted to various time slots in reference to clock and scan pattern. This feature of the laser diode allows triggering the laser pulse on the rising or the falling edge of the clock. Therefore, it is possible to choose the stage of the flip-flop in which the fault injection should occur. It is also demonstrated that the technique is able to identify the most sensitive signal condition for fault injection with a better time resolution than the pulse width of the laser, a significant improvement for failure analysis of integrated circuits.

Emerging Techniques for the Characterization of Nano-Mechanical Properties of Integrated Circuit Components

2008 ◽  
Author(s):  
Nicholas Randall ◽  
Rahul Premachandran Nair
Keyword(s):  
Mechanical Properties ◽  
Quality Control ◽  
Integrated Circuits ◽  
Integrated Circuit ◽  
Manufacturing Process ◽  
Solder Bumps ◽  
Initial Work ◽  
Circuit Components ◽  
Materials Used

Abstract With the growing complexity of integrated circuits (IC) comes the issue of quality control during the manufacturing process. In order to avoid late realization of design flaws which could be very expensive, the characterization of the mechanical properties of the IC components needs to be carried out in a more efficient and standardized manner. The effects of changes in the manufacturing process and materials used on the functioning and reliability of the final device also need to be addressed. Initial work on accurately determining several key mechanical properties of bonding pads, solder bumps and coatings using a combination of different methods and equipment has been summarized.

Dynamic Laser Delay Variation Mapping (DVM) Implementations and Applications

2005 ◽  
Author(s):  
Kevin Sanchez ◽  
Romain Desplats ◽  
Philippe Perdu ◽  
Felix Beaudoin ◽  
Sylvain Dudit ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Functional Tests ◽  
Laser Stimulation ◽  
Application Field ◽  
Defect Localization ◽  
Delay Variation

Abstract In this paper we report on the application field of Dynamic Laser Stimulation (DLS) techniques to Integrated Circuit (IC) analysis. The effects of thermal and photoelectric laser stimulation on ICs are presented. Implementations, practical considerations and applications are presented for techniques based on functional tests like Soft Defect Localization (SDL) and Laser Assisted Device Alteration (LADA). A new methodology, Delay Variation Mapping (DVM), will also be presented and discussed.

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