Turning Sample Into (Re)Solution—Focused Ion Beam Shaped Solid Immersion Lenses

2015 ◽  
Author(s):  
Philipp Scholz ◽  
Michael Sadowski ◽  
Christian Boit ◽  
Sebastian Kupijai ◽  
Marvin Henniges ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Focused Ion Beam ◽  
Photonic Integrated Circuits ◽  
Ion Beam ◽  
Signal Transmission ◽  
Optical Signal ◽  
Analysis Process ◽  
First Case ◽  
Solution Focused

Abstract This work is a unique solution for enhancing optical failure analysis and optical signal transmission. Optical failure analysis remains to be a vital part of the analysis process, despite shrinking feature sizes and challenging package technologies. The presented optical signal transmission supports the development of photonic integrated circuits. The key component is a Focused Ion Beam (FIB) process which shapes optical lenses out of the sample material leading to an improvement in lateral resolution and signal transmission. Two cases are shown that demonstrate these improvements. The first case is an optical backside analysis in a spatially confined opening of a package where other Solid Immersion Lens (SIL) systems could not be applied. It offers an improvement in spatial resolution by a factor of 2, down to a FWHM of 387 nm. The second case is a novel application for FIB shaped lenses aiming at photonic integrated circuits. This lens is created out of the isolating frontside and improves the grating coupler efficiency by a factor of 4.1.

Direct Imaging of Device Characteristics In a Focused ion Beam System

1998 ◽  
Vol 4 (S2) ◽  
pp. 652-653 ◽  
Author(s):  
A. N. Campbell ◽  
J. M. Soden
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Cross Sections ◽  
Material Removal ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Yield Enhancement ◽  
The Past ◽  
Design Changes ◽  
Design Debugging

A great deal can be learned about integrated circuits (ICs) and microelectronic structures simply by imaging them in a focused ion beam (FIB) system. FIB systems have evolved during the past decade from something of a curiosity to absolutely essential tools for microelectronics design verification and failure analysis. FIB system capabilities include localized material removal, localized deposition of conductors and insulators, and imaging. A major commercial driver for FIB systems is their usefulness in the design debugging cycle by (1) rewiring ICs quickly to test design changes and (2) making connection to deep conductors to facilitate electrical probing of complex ICs. FIB milling is also used for making precision cross sections and for TEM sample preparation of microelectronic structures for failure analysis and yield enhancement applications.

A Transmission X-ray Microscope (TXM) for Non-destructive 3D Imaging of ICs at Sub-100 nm Resolution

2002 ◽  
Author(s):  
Steve Wang ◽  
Frederick Duewer ◽  
Shashidar Kamath ◽  
Christopher Kelly ◽  
Alan Lyon ◽  
...  
Keyword(s):  
Electron Microscopy ◽  
Integrated Circuits ◽  
Failure Analysis ◽  
Focused Ion Beam ◽  
Process Development ◽  
Imaging System ◽  
Ion Beam ◽  
Layer By Layer ◽  
X Ray ◽  
Submicron Structures

Abstract Xradia has developed a laboratory table-top transmission x-ray microscope, TXM 54-80, that uses 5.4 keV x-ray radiation to nondestructively image buried submicron structures in integrated circuits with at better than 80 nm 2D resolution. With an integrated tomographic imaging system, a series of x-ray projections through a full IC stack, which may include tens of micrometers of silicon substrate and several layers of Cu interconnects, can be collected and reconstructed to produce a 3D image of the IC structure at 100 nm resolution, thereby allowing the user to detect, localize, and characterize buried defects without having to conduct layer by layer deprocessing and inspection that are typical of conventional destructive failure analysis. In addition to being a powerful tool for both failure analysis and IC process development, the TXM may also facilitate or supplant investigations using scanning electron microscopy (SEM), transmission electron microscopy (TEM), and focused ion beam (FIB) tools, which generally require destructive sample preparation and a vacuum environment.

scholarly journals Die Backside FIB Preparation for Identification and Characterization of Metal Voids

1999 ◽  
Author(s):  
Ann N. Campbell ◽  
William F. Filter ◽  
Nicholas Antoniou
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Cross Sections ◽  
Integrated Circuit ◽  
Flip Chip ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Milling Process ◽  
Plan View ◽  
Metal Interconnects

Abstract Both the increased complexity of integrated circuits, resulting in six or more levels of integration, and the increasing use of flip-chip packaging have driven the development of integrated circuit (IC) failure analysis tools that can be applied to the backside of the chip. Among these new approaches are focused ion beam (FIB) tools and processes for performing chip edits/repairs from the die backside. This paper describes the use of backside FIB for a failure analysis application rather than for chip repair. Specifically, we used FIB technology to prepare an IC for inspection of voided metal interconnects (“lines”) and vias. Conventional FIB milling was combined with a superenhanced gas assisted milling process that uses XeF2 for rapid removal of large volumes of bulk silicon. This combined approach allowed removal of the TiW underlayer from a large number of M1 lines simultaneously, enabling rapid localization and plan view imaging of voids in lines and vias with backscattered electron (BSE) imaging in a scanning electron microscope (SEM). Sequential cross sections of individual voided vias enabled us to develop a 3D reconstruction of these voids. This information clarified how the voids were formed, helping us identify the IC process steps that needed to be changed.

Pulse Laser Ablation Techniques for IC Package Substrate Modifications and Validation

2016 ◽  
Author(s):  
Matthew M. Mulholland ◽  
Ahmed A. Helmy ◽  
Anthony V. Dao
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Pulse Laser ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Back Side ◽  
Front Side ◽  
Local Approach ◽  
Ic Package ◽  
Level Analysis

Abstract Post silicon validation techniques specifically Focused Ion Beam (FIB) circuit editing and Failure Analysis (FA) require sample preparation on Integrated Circuits (IC). Although these preparation techniques are typically done globally across the encapsulated and silicon packaging materials, in some scenarios with tight mechanical or thermal boundary conditions, only a local approach can be attempted for the analysis. This local approach to access the underlying features, such as circuits, solder bumps, and electrical traces can be divided into two modification approaches. The back side approach is typically done for die level analysis by de-processing through encapsulated mold compound and silicon gaining access to the silicon transistor level. On the other hand, the front side approach is typically used for package level analysis by de-processing the ball grid array (BGA) and package substrate layers. Both of these local de-processing approaches can be done by using the conventional Laser Chemical Etching (LCE) platforms. The focus of this paper will be to investigate a front side modification approach to provide substrate material removal solutions. Process details and techniques will be discussed to gain access to metal signals for further failure analysis and debug. A pulse laser will be used at various processing stages to de-process IC package substrate materials.

scholarly journals A Quantitative Method for Measuring Remaining Silicon Thickness during XeF2 FIB Trenching for Backside Circuit Operations

2017 ◽  
Author(s):  
G.P. Salazar ◽  
R.J. Shul ◽  
S.N. Ball ◽  
M.J. Rye ◽  
B.S. Phillips ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Silicon Substrate ◽  
Quantitative Method ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Quantitative Measure ◽  
Mechanical Methods ◽  
Silicon Thickness

Abstract Backside circuit edit (CE) remains a crucial failure analysis (FA) capability, enabling design modifications on advanced integrated circuits. [1-9] A key requirement of this activity is to approach the active transistor layer of the silicon through the removal of the silicon substrate without exposing or damaging critical transistor features. Several methods have been previously developed to enable or assist with the process with either global or locally targeted techniques for thinning the silicon substrate. These methods employ mechanical methods, laser based techniques (continuous or pulsed), or chemical assisted focused ion beam (FIB) etching to accomplish the thinning. Each of these methods presents different strengths and weaknesses, from their reliability to complexity, but very few techniques provide a precise and accurate quantitative measure of the remaining silicon thickness (RST). Here, we will discuss the use of a FIB with XeF2 for backside Si removal, and the development of an in-situ, accurate measurement of RST.

Analysis of DC Failure in Advanced Memory Devices Using Nanoprobing and Scanning Capacitance Microscopy

2007 ◽  
Author(s):  
Jen-Lang Lue ◽  
Chin-Shun Lin ◽  
Atup Chiou ◽  
Hsuen-Cheng Liao ◽  
Hsienwen Liu ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Leakage Current ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Doping Profile ◽  
Memory Devices ◽  
Cross Sectional ◽  
Analysis Process ◽  
Leakage Path ◽  
Current Voltage

Abstract This paper discusses the failure analysis process of a DC failure using an in-FIB (Focused Ion Beam) nanoprobing technique with four probes and a scanning capacitance microscope (SCM) in advanced DRAM devices. Current-Voltage (I-V) curves measured by the nanoprobing technique indicate the curve of the failed device is different from that of the normal device. The failed device causes a high leakage current in the test. The cross-sectional 2-D doping profile of SCM verifies the region of the P-Well has shifted to create a leakage path that causes this failure.

Echelle grating – curved wave-guide demultiplexer for photonic integrated circuits

1992 ◽  
Vol 70 (10-11) ◽  
pp. 928-930
Author(s):  
M. Fallahi ◽  
K. A. McGreer ◽  
A. Delage ◽  
R. Normandin ◽  
I. M. Templeton ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Focused Ion Beam ◽  
Photonic Integrated Circuits ◽  
Ion Beam ◽  
Waveguide Structure ◽  
Active Components ◽  
Channel Spacing ◽  
Ion Beam Lithography ◽  
Echelle Grating ◽  
Wave Guides

A grating spectrometer integrated with curved output wave guides was designed and fabricated in GaAs–AlGaAs waveguide structure for use in the 1 μm wavelength range. By incorporating curved wave guides, a larger separation between output facets was obtained. This is desirable for future integration. High-quality patterns were fabricated by focused ion beam lithography and reactive ion etching. Eight outputs with a channel spacing of 2 nm were obtained. The potential of the structure for integration with active components is discussed.

Domain patterning thin crystalline ferroelectric film with focused ion beam for nonlinear photonic integrated circuits

2006 ◽  
Vol 100 (10) ◽  
pp. 106103 ◽  
Author(s):  
Xijun Li ◽  
Kazuya Terabe ◽  
Hideki Hatano ◽  
Huarong Zeng ◽  
Kenji Kitamura
Keyword(s):  
Integrated Circuits ◽  
Focused Ion Beam ◽  
Photonic Integrated Circuits ◽  
Ion Beam ◽  
Ferroelectric Film

Fluorocarbon Precursor for High Aspect Ratio via Milling in Focused Ion Beam Modification of Integrated Circuits

2004 ◽  
Author(s):  
Valery Ray
Keyword(s):  
Side Effects ◽  
Aspect Ratio ◽  
Integrated Circuits ◽  
High Aspect Ratio ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Enabling Technology ◽  
Si Substrate ◽  
Ion Beam Modification ◽  
The Past

Abstract Gas Assisted Etching (GAE) is the enabling technology for High Aspect Ratio (HAR) circuit access via milling in Focused Ion Beam (FIB) circuit modification. Metal interconnect layers of microelectronic Integrated Circuits (ICs) are separated by Inter-Layer Dielectric (ILD) materials, therefore HAR vias are typically milled in dielectrics. Most of the etching precursor gases presently available for GAE of dielectrics on commercial FIB systems, such as XeF2, Cl2, etc., are also effective etch enhancers for either Si, or/and some of the metals used in ICs. Therefore use of these precursors for via milling in dielectrics may lead to unwanted side effects, especially in a backside circuit edit approach. Making contacts to the polysilicon lines with traditional GAE precursors could also be difficult, if not impossible. Some of these precursors have a tendency to produce isotropic vias, especially in Si. It has been proposed in the past to use fluorocarbon gases as precursors for the FIB milling of dielectrics. Preliminary experimental evaluation of Trifluoroacetic (Perfluoroacetic) Acid (TFA, CF3COOH) as a possible etching precursor for the HAR via milling in the application to FIB modification of ICs demonstrated that highly enhanced anisotropic milling of SiO2 in HAR vias is possible. A via with 9:1 aspect ratio was milled with accurate endpoint on Si and without apparent damage to the underlying Si substrate.

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