Analysis of DC Failure in Advanced Memory Devices Using Nanoprobing and Scanning Capacitance Microscopy

2007 ◽  
Author(s):  
Jen-Lang Lue ◽  
Chin-Shun Lin ◽  
Atup Chiou ◽  
Hsuen-Cheng Liao ◽  
Hsienwen Liu ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Leakage Current ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Doping Profile ◽  
Memory Devices ◽  
Cross Sectional ◽  
Analysis Process ◽  
Leakage Path ◽  
Current Voltage

Abstract This paper discusses the failure analysis process of a DC failure using an in-FIB (Focused Ion Beam) nanoprobing technique with four probes and a scanning capacitance microscope (SCM) in advanced DRAM devices. Current-Voltage (I-V) curves measured by the nanoprobing technique indicate the curve of the failed device is different from that of the normal device. The failed device causes a high leakage current in the test. The cross-sectional 2-D doping profile of SCM verifies the region of the P-Well has shifted to create a leakage path that causes this failure.

High-Throughput, Site-Specific Sample Prep of Ultra-Thin TEM Lamella for Process Metrology and Failure Analysis

2012 ◽  
Author(s):  
Roger Alvis ◽  
Jeff Blackwood ◽  
Sang-Hoon Lee ◽  
Matthew Bray
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
Process Monitoring ◽  
High Throughput ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Memory Devices ◽  
Site Specific ◽  
Critical Dimensions ◽  
Tem Lamella

Abstract Semiconductor devices with critical dimensions less than 20nm are now being manufactured in volume. A challenge facing the failure analysis and process-monitoring community is two-fold. The first challenge of TEM sample prep of such small devices is that the basic need to end-point on a feature-of-interest pushes the imaging limit of the instrument being used to prepare the lamella. The second challenge posed by advanced devices is to prepare an artifact-free lamella from non-planar devices such as finFETs as well as from structures incorporating ‘non-traditional’ materials. These challenges are presently overcome in many advanced logic and memory devices in the focused ion beam-based TEM sample preparation processes by inverting the specimen prior to thinning to electron transparency. This paper reports a highthroughput method for the routine preparation of artifact-free TEM lamella of 20nm thickness, or less.

Failure Analysis Strategies for Multistacked Memory Devices with TSV Interconnects

2015 ◽  
Author(s):  
Frank Altmann ◽  
Christian Grosse ◽  
Falk Naumann ◽  
Jens Beyersdorfer ◽  
Tony Veches
Keyword(s):  
Failure Analysis ◽  
Focused Ion Beam ◽  
Failure Modes ◽  
Ion Beam ◽  
Memory Devices ◽  
Metallographic Cross Section ◽  
Electron Beam Induced Current ◽  
Thermal Simulations ◽  
Lock In ◽  
Non Destructive

Abstract In this paper we will demonstrate new approaches for failure analysis of memory devices with multiple stacked dies and TSV interconnects. Therefore, TSV specific failure modes are studied on daisy chain test samples. Two analysis flows for defect localization implementing Electron Beam Induced Current (EBAC) imaging and Lock-in-Thermography (LIT) as well as adapted Focused Ion Beam (FIB) preparation and defect characterization by electron microscopy will be discussed. The most challenging failure mode is an electrical short at the TSV sidewall isolation with sub-micrometer dimensions. It is shown that the leakage path to a certain TSV within the stack can firstly be located by applying LIT to a metallographic cross section and secondly pinpointing by FIB/SEM cross-sectioning. In order to evaluate the potential of non-destructive determination of the lateral defect position, as well as the defect depth from only one LIT measurement, 2D thermal simulations of TSV stacks with artificial leakages are performed calculating the phase shift values per die level.

scholarly journals Highly Rectifying Heterojunctions Formed by Annealed ZnO Nanorods on GaN Substrates

Nanomaterials ◽  
2020 ◽  
Vol 10 (3) ◽  
pp. 508 ◽  
Author(s):  
Stanislav Tiagulskyi ◽  
Roman Yatskiv ◽  
Hana Faitová ◽  
Šárka Kučerová ◽  
David Roesel ◽  
...  
Keyword(s):  
Electrical Properties ◽  
Leakage Current ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Zno Nanorods ◽  
Carrier Injection ◽  
Ion Beam Lithography ◽  
Current Voltage ◽  
P Type ◽  
Surface Leakage

We study the effect of thermal annealing on the electrical properties of the nanoscale p-n heterojunctions based on single n-type ZnO nanorods on p-type GaN substrates. The ZnO nanorods are prepared by chemical bath deposition on both plain GaN substrates and on the substrates locally patterned by focused ion beam lithography. Electrical properties of single nanorod heterojunctions are measured with a nanoprobe in the vacuum chamber of a scanning electron microscope. The focused ion beam lithography provides a uniform nucleation of ZnO, which results in a uniform growth of ZnO nanorods. The specific configuration of the interface between the ZnO nanorods and GaN substrate created by the focused ion beam suppresses the surface leakage current and improves the current-voltage characteristics. Further improvement of the electrical characteristics is achieved by annealing of the structures in nitrogen, which limits the defect-mediated leakage current and increases the carrier injection efficiency.

Identification of an IDDQ Failure Mechanism Using a Variety of Front and Backside Analytical Techniques

2003 ◽  
Author(s):  
Jim Shearer ◽  
Kim Le ◽  
Xiaoyu Yang ◽  
Monty Cleeves ◽  
Al Meeks
Keyword(s):  
Failure Analysis ◽  
Focused Ion Beam ◽  
Metal Layer ◽  
Ion Beam ◽  
Photon Emission ◽  
Analytical Techniques ◽  
Cmos Process ◽  
Microscopy Imaging ◽  
Leakage Path ◽  
Dual Beam

Abstract This article presents a case study to solve an IDDQ leakage problem using a variety of failure analysis techniques on a product. The product is fabricated using a 3-metal-layer 0.25 μm CMOS process with the addition of Matrix's proprietary 3-D memory layers. The failure analysis used both top and backside analytical techniques, including liquid crystal, photon emission microscopy from both front and back, dual-beam focused ion beam cross-sectioning, field emission scanning electron microscopy imaging, parallel-lap/passive voltage contrast, microprobing of parallel-lapped samples, and scanning capacitance microscopy. The article discusses how the application of each of the techniques narrowed down the search for this IDDQ leakage path. This leakage path was eliminated using the two corrective actions: The resist is pre-treated prior to ion implantation to produce a consistent resist sidewall profile; and the Nwell boundaries were adjusted in the next Nwell mask revision.

Failure Analysis of Tungsten Stud Defect from the CMP Process

2000 ◽  
Author(s):  
K. Takagi ◽  
Y. Kohno ◽  
S. Nukii
Keyword(s):  
Electron Microscopy ◽  
Failure Analysis ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Electrical Characterization ◽  
Open Circuit ◽  
Physical Analysis ◽  
Metal Line ◽  
Cross Sectional ◽  
Defect Isolation

Abstract This paper describes a failure analysis that effectively combined multiple analytic techniques to find the cause of I/O leakage in a flawed chip produced for an OEM (Original Equipment Manufacturer) product. Internal probing was initially used for defect isolation and a Tungsten (W) stud open circuit flaw was isolated by electrical characterization with internal probing. SEM (Scanning Electron Microscopy), TEM (Transmission Electron Microscopy, and FE-AES (Field Emission Auger Electron Spectroscopy) analysis with FIB (Focused Ion Beam) preparation were used for physical analysis. Cross-sectional SEM and TEM observations showed a gap with foreign material (FM) between the bottom of the metal line and the top of the W stud, possibly from the W CMP (chemical mechanical polish) process. FE-AES is effective for the analysis of light materials and their chemical composition, so a flat milling FIB process was used to prepare a cross-section for FE-AES analysis of the FM and the interfaces of the open defect. The spectra showed that the FM was traceable to the W CMP process. From these analytical results and problem reproduction experiments in the W CMP process on the manufacturing line, the failure mechanism was identified.

Reduction of Whisker-Originated Short between W Polymetal and Contact Plug

2001 ◽  
Vol 670 ◽  
Author(s):  
Yasushi Akasaka ◽  
Hiroshi Suzuki ◽  
Yuji Yokoyama ◽  
Nobuaki Yasutake ◽  
Hitomi Yasutake ◽  
...  
Keyword(s):  
High Temperature ◽  
Leakage Current ◽  
Focused Ion Beam ◽  
Whisker Growth ◽  
Ion Beam ◽  
The Self ◽  
Cross Sectional ◽  
Gate Electrodes ◽  
High Temperature Processing ◽  
First Time

ABSTRACTWhisker-originated short in the self-aligned contact (SAC) W polymetal gate was directly observed for the first time. Short points between gate electrodes and poly-Si plugs in the test structure were identified by emission microscope and cross-sectional TEM samples of those points were made by using focused ion beam (FIB).Whiskers are formed during high-temperature processing such as LP-CVD SiN. We have proposed that NH3 de-oxidation step inserted in the SiN deposition sequence is effective for suppressing whisker growth. [1] In this study it was also confirmed that 600°C NH 3 pre-flow improved leakage current between gate electrode and contact plugs.

Identification and Analysis of Parasitic Depletion Mode Leakage in a Memory Select Transistor

2000 ◽  
Author(s):  
Jim B. Colvin ◽  
Anirban Roy
Keyword(s):  
Failure Analysis ◽  
Spatial Resolution ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Electrical Contact ◽  
Electrical Behavior ◽  
Embedded Memory ◽  
Electrical Parameters ◽  
Leakage Path ◽  
Field Oxide

Abstract Low yield was reported for a non-volatile embedded memory array. In one case, the n-channel transistor was observed to exhibit single bit OFF leakage in a 32K array. In another case, there was general leakage observed between drain junctions of neighboring transistors, even though these were isolated by field oxide. The objective of the failure analysis described in this article was to characterize the electrical behavior of the leakage and determine the exact location and cause of the leakage. Focused Ion Beam was used to make electrical contact to drain regions, which lacked a contact for microprobing. Once the electrical parameters were obtained, photoemission analysis was performed with modified probes for higher spatial resolution to pinpoint the leakage path. Finally, scanning capacitance microscopy methods were used to prove the presence of the n-type depletion path. Very clear and positive confirmation of the presence of the parasitic n-type dopant was confirmed.

Turning Sample Into (Re)Solution—Focused Ion Beam Shaped Solid Immersion Lenses

2015 ◽  
Author(s):  
Philipp Scholz ◽  
Michael Sadowski ◽  
Christian Boit ◽  
Sebastian Kupijai ◽  
Marvin Henniges ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Focused Ion Beam ◽  
Photonic Integrated Circuits ◽  
Ion Beam ◽  
Signal Transmission ◽  
Optical Signal ◽  
Analysis Process ◽  
First Case ◽  
Solution Focused

Abstract This work is a unique solution for enhancing optical failure analysis and optical signal transmission. Optical failure analysis remains to be a vital part of the analysis process, despite shrinking feature sizes and challenging package technologies. The presented optical signal transmission supports the development of photonic integrated circuits. The key component is a Focused Ion Beam (FIB) process which shapes optical lenses out of the sample material leading to an improvement in lateral resolution and signal transmission. Two cases are shown that demonstrate these improvements. The first case is an optical backside analysis in a spatially confined opening of a package where other Solid Immersion Lens (SIL) systems could not be applied. It offers an improvement in spatial resolution by a factor of 2, down to a FWHM of 387 nm. The second case is a novel application for FIB shaped lenses aiming at photonic integrated circuits. This lens is created out of the isolating frontside and improves the grating coupler efficiency by a factor of 4.1.

Automated Diagonal Slice and View Solution for 3D Device Structure Analysis

2018 ◽  
Author(s):  
Sang Hoon Lee ◽  
Jeff Blackwood ◽  
Stacey Stone ◽  
Michael Schmidt ◽  
Mark Williamson ◽  
...  
Keyword(s):  
Cross Section ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Image Data ◽  
Planar Surface ◽  
Device Structure ◽  
Cross Sectional ◽  
Device Structures ◽  
The Cross ◽  
Planar Analysis

Abstract The cross-sectional and planar analysis of current generation 3D device structures can be analyzed using a single Focused Ion Beam (FIB) mill. This is achieved using a diagonal milling technique that exposes a multilayer planar surface as well as the cross-section. this provides image data allowing for an efficient method to monitor the fabrication process and find device design errors. This process saves tremendous sample-to-data time, decreasing it from days to hours while still providing precise defect and structure data.

TEM Sample Preparation Tricks for Advanced DRAMs

2015 ◽  
Author(s):  
Ching Shan Sung ◽  
Hsiu Ting Lee ◽  
Jian Shing Luo
Keyword(s):  
Electron Microscopy ◽  
Transmission Electron Microscopy ◽  
Sample Preparation ◽  
Integrated Circuit ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Tem Analysis ◽  
Cross Sectional ◽  
Transmission Electron ◽  
Characterization Of Materials

Abstract Transmission electron microscopy (TEM) plays an important role in the structural analysis and characterization of materials for process evaluation and failure analysis in the integrated circuit (IC) industry as device shrinkage continues. It is well known that a high quality TEM sample is one of the keys which enables to facilitate successful TEM analysis. This paper demonstrates a few examples to show the tricks on positioning, protection deposition, sample dicing, and focused ion beam milling of the TEM sample preparation for advanced DRAMs. The micro-structures of the devices and samples architectures were observed by using cross sectional transmission electron microscopy, scanning electron microscopy, and optical microscopy. Following these tricks can help readers to prepare TEM samples with higher quality and efficiency.

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