Intra-Device Defect Localization through EBIC/EBAC Combined with Electrical Nanoprobing for FinFET Devices Composed of Multiple Sub-Elements

2016 ◽  
Author(s):  
Daminda H. Dahanayaka ◽  
Daniel A. Bader ◽  
Dennis P. Prevost ◽  
Michael T. Coster ◽  
Erik F. Mccullen ◽  
...  
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
Cross Sectional ◽  
Plan View ◽  
Nanoelectronic Devices ◽  
Defect Localization ◽  
Depth Sensitivity ◽  
Sectional Analysis ◽  
Technology Nodes ◽  
Sem Analyses

Abstract Physical failure analysis of nanoelectronic devices is typically performed using plan view or cross-sectional TEM, SEM or SPM techniques. While plan view SPM and SEM analyses are limited by the depth sensitivity of the technique, cross-sectional analysis requires at least approximate localization of the fail location within the device for effective sample preparation. Multi-finger wide 2D planar devices and multi-FIN 3D devices are structures which require an additional step in pinpointing the fail area within the device. This paper describes successful use of EBIC/EBAC techniques to localize the fail location within such devices in both the 22 nm and 14 nm technology nodes.

A Novel Method for the Specified Site Planar View TEM Sample Preparation

2014 ◽  
Author(s):  
Shuqing Duan ◽  
Yanli Zhao ◽  
Ming Li
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
The Novel ◽  
Plan View ◽  
Site Specific ◽  
Transmission Electron ◽  
Novel Method ◽  
Failure Location ◽  
Rate Of Failure ◽  
Technology Nodes

Abstract This paper reports a novel method for site specific plan view transmission electron microscopy (TEM) sample preparation. The detailed procedure is introduced step by step. To demonstrate the practicality of this technique in failure analysis, case studies on 45nm and below technology nodes using the novel method are reported. The results showed that the method is very useful for the analysis of the specified failure location and is helpful to improve the success rate of failure analysis.

A Selected Area Planar TEM (SAPTEM) Sample Preparation Procedure for Failure Analysis of Integrated Circuits

1998 ◽  
Author(s):  
S. Subramanian ◽  
P. Schani ◽  
E. Widener ◽  
P. Liston ◽  
J. Moss ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Sample Preparation ◽  
Failure Analysis ◽  
Cross Section ◽  
Ion Beam ◽  
Preparation Technique ◽  
Mechanical Grinding ◽  
Cross Sectional ◽  
Plan View ◽  
The Cross

Abstract A selected area planar TEM (SAPTEM) sample preparation technique for failure analysis of integrated circuits using a transmission electron microscope has been developed. The technique employs a combination of mechanical grinding, selective wet/dry chemical etching (if required) and a two step focused ion beam IIFIB) milling. The mechanical grinding steps include: (a) a backside grind to achieve a die thickness less than 30 µm, (b) the support half ring glue, and (c) a cross-section grind from one side to reach less than 35 pm to the failing site. A selective wet or dry chemical etch is applied before, between,, or after FIB thinning depending on the nature of problem and device components. The FIB milling steps involve: (is) a high ion current cross-sectional cut to reach as close as 5-8 µm to the area of interest (b) a final planar thinning with the ion beam parallel to the surface of the die. The plan view procedure offers unique geometric advantage over the cross-section method for failure analysis of problems that are limited to silicon or certain layers of the device. Iln the cross-sectional approach, a thin section (thickness less than 250 µm) of a device is available for failure analysis, whereas in the planar procedure a 20 µm2 area of any layer (thickness less than 250 µm) of the device is available. The above advantage has been successfully exploited to identify and solve the following prablems in fast static random access memories (FSRAM): (i) random gateoxide rupture that resulted in single bit failures, (ii) random dislocations from the buried contact trenching that caused single bit failures and general silicon defectivity (e.g. implant damage and spacer edge defects), and (iii) interracial reactions.

Impacts of Sample Preparation Methodology on TEM Failure Analysis of Advanced Semiconductor Devices

2011 ◽  
Author(s):  
Yongkai Zhou ◽  
Jie Zhu ◽  
Han Wei Teo ◽  
ACT Quah ◽  
Lei Zhu ◽  
...  
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
Case Studies ◽  
Thickness Measurement ◽  
Interface Roughness ◽  
Silicide Formation ◽  
Cross Sectional ◽  
Inspection Method ◽  
Low Mass

Abstract In this paper, two failure analysis case studies are presented to demonstrate the importance of sample preparation procedures to successful failure analyses. Case study 1 establishes that Palladium (Pd) cannot be used as pre-FIB coating for SiO2 thickness measurement due to the spontaneously Pd silicide formation at the SiO2/Si interface. Platinum (Pt) is thus recommended, in spite of the Pt/SiO2 interface roughness, as the pre-FIB coating in this application. In the second case study, the dual-directional TEM inspection method is applied to characterize the profile of the “invisible” tungsten residue defect. The tungsten residue appears invisible in the planeview specimen due to the low mass-thickness contrast. It is then revealed in the cross-sectional TEM inspection.

A New Method of Wafer Level Plan View TEM Sample Preparation by DualBeam

2008 ◽  
Author(s):  
Hyoung H. Kang ◽  
Michael A. Gribelyuk ◽  
Oliver D. Patterson ◽  
Steven B. Herschbein ◽  
Corey Senowitz
Keyword(s):  
Sample Preparation ◽  
Ex Situ ◽  
Wafer Level ◽  
Cross Sectional ◽  
Plan View ◽  
Manufacturing Line ◽  
Transmission Electron ◽  
Thin Lamella ◽  
Preparation Techniques

Abstract Cross-sectional style transmission electron microscopy (TEM) sample preparation techniques by DualBeam (SEM/FIB) systems are widely used in both laboratory and manufacturing lines with either in-situ or ex-situ lift out methods. By contrast, however, the plan view TEM sample has only been prepared in the laboratory environment, and only after breaking the wafer. This paper introduces a novel methodology for in-line, plan view TEM sample preparation at the 300mm wafer level that does not require breaking the wafer. It also presents the benefit of the technique on electrically short defects. The methodology of thin lamella TEM sample preparation for plan view work in two different tool configurations is also presented. The detailed procedure of thin lamella sample preparation is also described. In-line, full wafer plan view (S)TEM provides a quick turn around solution for defect analysis in the manufacturing line.

Specific Area Planar and Cross-Sectional Lift-Out Techniques: Procedures and Novel Applications

2000 ◽  
Author(s):  
Raghaw S. Rai ◽  
Swaminathan Subramanian ◽  
Stewart Rose ◽  
James Conner ◽  
Phil Schani ◽  
...  
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
Integrated Circuit ◽  
Ion Beam ◽  
Specific Area ◽  
Cross Sectional ◽  
Site Specific ◽  
Focussed Ion Beam ◽  
Lattice Images ◽  
Novel Applications

Abstract Conventional focussed ion beam (FIB) based specific area transmission electron microscopy (TEM) sample preparation techniques usually requires complex grinding and gluing steps before final FIB thinning of the sample to electron transparency (<0.25 μm). A novel technique known as lift-out, plucking or pullout method that eliminates all the pre-FIB sample preparation has been developed for specific area TEM sample preparation by several authors. The advantages of the lift-out procedure include reduced sample preparation time and possibility of specific area TEM sample preparation of most components of integrated circuit with almost no geometric or dimensional limitations. In this paper, details of liftout method, developed during the present work, for site specific x-sectional and a new site specific planar sample preparation are described. Various methodologies are discussed to maximize the success rate by optimizing the factors that affect the technique. In failure analysis, the geometric and dimensional flexibility offered by the lift-out technique can be used to prepare specific area TEM sample of back thinned die, small particles and packaged parts. Such novel applications of lift-out technique in failure analysis are discussed with the examples of TEM results obtained from GaAs and Si based devices. Importantly, it was possible to obtain high resolution lattice images from the lift-out samples transferred on holey carbon supported 3mm copper grids.

The Challenge and Methods of TEM Cross-Sectioning of < 0.25 Micron Plugs

1998 ◽  
Vol 523 ◽  
Author(s):  
C. Amy Hunt ◽  
Yuhong Zhang ◽  
David Su
Keyword(s):  
Electron Microscopy ◽  
Transmission Electron Microscopy ◽  
Sample Preparation ◽  
Failure Analysis ◽  
Cross Section ◽  
Adhesion Layer ◽  
Cross Sectional ◽  
Transmission Electron ◽  
Sectional Plane ◽  
Preparation Techniques

AbstractTransmission electron microscopy (TEM) is a useful tool in process evaluation and failure analysis for semiconductor industries. A common focus of semiconductor TEM analyses is metalization vias (plugs) and it is often desirable to cross-section through a particular one. If the cross-sectional plane deviates away from the center of the plug, then the thin adhesion layer around the plug will be blurred by surrounding materials such as the inter-layer dielectric and the plug material. The importance of these constraints, along with the difficulty of precision sample preparation, has risen sharply as feature sizes have fallen to 0.25 μm and below. The suitability of common sample preparation techniques for these samples is evaluated.

Backside EBIRCH Defect Localization for Advanced Flip-Chip Failure Analysis

2021 ◽  
Author(s):  
Chuan Zhang ◽  
Jane Y. Li ◽  
John Aguada ◽  
Howard Marks
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
Flip Chip ◽  
Flip Chips ◽  
Defect Localization ◽  
Localization Approach

Abstract This paper introduced a novel defect localization approach by performing EBIRCH isolation from backside of flip-chips. Sample preparation and probing consideration was discussed, and then a case study was used to illustrate how the backside EBIRCH technique provides a powerful solution in capturing and root-causing subtle defects in challenging flip-chip failures.

3-D Defect Characterization using Plan View and Cross-Sectional TEM/STEM Analysis

2005 ◽  
Author(s):  
Terrence J. Stark ◽  
Phillip E. Russell ◽  
Corey Nevers
Keyword(s):  
Optoelectronic Device ◽  
Three Dimensions ◽  
Defect Characterization ◽  
Stem Analysis ◽  
Cross Sectional ◽  
Plan View ◽  
Practical Tool ◽  
Crystalline Defect ◽  
Sectional Analysis ◽  
Complex Semiconductor

Abstract The primary objectives of failure analysis on structurally complex semiconductor devices are often to determine a defect's location and composition. Determining exactly how these defects propagate through a sample in three dimensions, to confirm a failure mode, is often elusive. This paper discusses characterizations of two defect types to illustrate a technique of sequentially imaging whisker type defects from orthogonal orientations using TEM/STEM. The first type is a high resistance short between two metal lines that is best imaged using STEM in order to observe subtle differences in material composition. The second is a crystalline dislocation through an optoelectronic device that is best observed using TEM. Details of resistive short characterization and crystalline defect characterization performed are provided. TEM/STEM has shown to be a practical tool for locating defects prior to cross sectional analysis. This allows defects to be located and characterized in three dimensions.

Volume Electrical Failure Analysis for Product-Specific Yield Enhancement

2010 ◽  
Author(s):  
Steven Kasapi ◽  
Joy Liao ◽  
Bruce Cory ◽  
Izak Kapilevich ◽  
Richard Portune ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Test Pattern ◽  
New Technology ◽  
Significant Benefit ◽  
Yield Enhancement ◽  
Specific Yield ◽  
Design Knowledge ◽  
Electrical Failure ◽  
Defect Localization ◽  
Technology Nodes

Abstract Yield on specific designs often falls far short of predicted yield, especially at new technology nodes. Product-specific yield ramp is particularly challenging because the defects are, by definition, specific to the design, and often require some degree of design knowledge to isolate the failure. Despite the wide variety of advanced electrical failure analysis (EFA) techniques available today, they are not routinely applied during yield ramp. EFA techniques typically require a significant amount of test pattern customization, fixturing modification, or design knowledge. Unless the problem is critical, there is usually not time to apply advanced EFA techniques during yield ramp, despite the potential of EFA to provide valuable defect insight. We present a volume-oriented workflow integrating a limited set of electrical failure analysis (EFA) techniques. We believe this workflow will provide significant benefit by improving defect localization and identification beyond what is available using test-based techniques.

Photon Emission Microscope as a Tool for 3-Dimensional Semiconductor Device Failure Analysis

2012 ◽  
Author(s):  
Steven J. Chun
Keyword(s):  
Failure Analysis ◽  
Semiconductor Device ◽  
Photon Emission ◽  
Three Dimensional ◽  
Analysis Method ◽  
Cross Sectional ◽  
3 Dimensional ◽  
Two Photon ◽  
Processing Times ◽  
Sectional Analysis

Abstract A three dimensional (3-D) photon emission failure analysis method has been developed to pinpoint failure sites or emission sites on the x, y, and z planes of a degraded diode. The 3-D analysis consists of a cross-sectioning step process on two adjacent sides of a diode utilizing two photon emission sites from respective sides of the die as a map. This process negates the uncertainty and long processing times during cross-sectional analysis to find minute defects in diodes.

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