scholarly journals Parallel Computation of CRC-Code on an FPGA Platform for High Data Throughput

Electronics ◽  
2021 ◽  
Vol 10 (7) ◽  
pp. 866
Author(s):  
Dat Tran ◽  
Shahid Aslam ◽  
Nicolas Gorius ◽  
George Nehmetallah
Keyword(s):  
Field Programmable Gate Array ◽  
High Data ◽  
Transmission Distance ◽  
Look Up Table ◽  
Data Throughput ◽  
Error Check ◽  
Field Programmable ◽  
Speed Up ◽  
Rapid Processing ◽  
Radiation Hard

With the rapid advancement of radiation hard imaging technology, space-based remote sensing instruments are becoming not only more sophisticated but are also generating substantially more amounts of data for rapid processing. For applications that rely on data transmitted from a planetary probe to a relay spacecraft to Earth, alteration or discontinuity in data over a long transmission distance is likely to happen. Cyclic Redundancy Check (CRC) is one of the most well-known package error check techniques in sensor networks for critical applications. However, serial CRC computation could be a bottleneck of the throughput in such systems. In this work, we design, implement, and validate an efficient hybrid look-up-table and matrix transformation algorithm for high throughput parallel computational unit to speed-up the process of CRC computation using both CPU and Field Programmable Gate Array (FPGA) with comparison of both methods.

scholarly journals VLSI implementation of Wallace Tree Multiplier using Ladner-Fischer Adder

2021 ◽  
Vol 14 (1) ◽  
pp. 22-31
Author(s):  
Kommalapati Monica ◽  
◽  
Dereddy Anuradha ◽  
Syed Rasheed ◽  
Barnala Shereesha ◽  
...  
Keyword(s):  
Power Consumption ◽  
Field Programmable Gate Array ◽  
Finite Impulse Response ◽  
Research Work ◽  
Industrial Applications ◽  
Booth Multiplier ◽  
Wallace Tree ◽  
Look Up Table ◽  
Field Programmable ◽  
Wallace Tree Multiplier

Nowadays, most of the application depends on arithmetic designs such as an adder, multiplier, divider, etc. Among that, multipliers are very essential for designing industrial applications such as Finite Impulse Response, Fast Fourier Transform, Discrete cosine transform, etc. In the conventional methods, different kind of multipliers such as array multiplier, booth multiplier, bough Wooley multiplier, etc. are used. These existing multipliers are occupied more area to operate. In this study, Wallace Tree Multiplier (WTM) is implemented to overcome this problem. Two kinds of multipliers have designed in this research work for comparison. At first, existing WTM is designed with normal full adders and half adders. Next, proposed WTM is designed using Ladner Fischer Adder (LFA) to improve the hardware utilization and reduce the power consumption. Field Programmable Gate Array (FPGA) performances such as slice Look Up Table (LUT), Slice Register, Bonded Input-Output Bios (IOB) and power consumption are evaluated. The proposed WTM-LFA architecture occupied 374 slice LUT, 193 slice register, 59 bonded IOB, and 26.31W power. These FPGA performances are improved compared to conventional multipliers such asModified Retiming Serial Multiplier (MRSM), Digit Based Montgomery Multiplier (DBMM), and Fast Parallel Decimal Multiplier (FPDM).

scholarly journals Efficient-Scheduling Parallel Multiplier-Based Ring-LWE Cryptoprocessors

Electronics ◽  
2019 ◽  
Vol 8 (4) ◽  
pp. 413 ◽  
Author(s):  
Tuy Nguyen Tan ◽  
Hanho Lee
Keyword(s):  
Field Programmable Gate Array ◽  
Path Delay ◽  
Hardware Complexity ◽  
Parallel Multiplier ◽  
Multiplication Operation ◽  
Encryption And Decryption ◽  
Field Programmable ◽  
Speed Up ◽  
Learning With Errors ◽  
Single Path

This paper presents a novel architecture for ring learning with errors (LWE) cryptoprocessors using an efficient approach in encryption and decryption operations. By scheduling multipliers to work in parallel, the encryption and decryption time are significantly reduced. In addition, polynomial multiplications are conducted using radix-2 and radix-8 multiple delay feedback (MDF) architecture-based number theoretic transform (NTT) multipliers to speed up the multiplication operation. To reduce the hardware complexity of an NTT multiplier, three bit-reverse operations during the NTT and inverse NTT (INTT) processes are removed. Polynomial additions in the ring-LWE encryption phase are also arranged to work simultaneously to reduce the latency. As a result, the proposed efficient-scheduling parallel multiplier-based ring-LWE cryptoprocessors can achieve higher throughput and efficiency compared with existing architectures. The proposed ring-LWE cryptoprocessors are synthesized and verified using Xilinx VIVADO on a Virtex-7 field programmable gate array (FPGA) board. With security parameters n = 512 and q = 12,289, the proposed cryptoprocessors using radix-2 single-path delay feedback (SDF), radix-2 MDF, and radix-8 MDF multipliers perform encryption in 4.58 μ s, 1.97 μ s, and 0.89 μ s, and decryption in 4.35 μ s, 1.82 μ s, and 0.71 μ s, respectively. A comparison of the obtained throughput and efficiency with those of previous studies proves that the proposed cryptoprocessors achieve a better performance.

Low‐power and area efficient binary coded decimal adder design using a look up table‐based field programmable gate array

2016 ◽  
Vol 10 (3) ◽  
pp. 163-172 ◽  
Author(s):  
Zarrin Tasnim Sworna ◽  
Mubin UlHaque ◽  
Nazma Tara ◽  
Hafiz Md. Hasan Babu ◽  
Ashis Kumar Biswas
Keyword(s):  
Low Power ◽  
Field Programmable Gate Array ◽  
Look Up Table ◽  
Field Programmable ◽  
Decimal Adder ◽  
Gate Array ◽  
Area Efficient

scholarly journals Hardware/software co-design for a parallel three-dimensional bresenham’s algorithm

2019 ◽  
Vol 9 (1) ◽  
pp. 148
Author(s):  
Sarmad Ismael ◽  
Omar Tareq ◽  
Yahya Taher Qassim
Keyword(s):  
Field Programmable Gate Array ◽  
Complete System ◽  
Line Drawing ◽  
Three Dimensional ◽  
End Point ◽  
Field Programmable ◽  
Speed Up ◽  
The One ◽  
Scan Conversion ◽  
Number Of Segments

<p>Line plotting is the one of the basic operations in the scan conversion. Bresenham’s line drawing algorithm is an efficient and high popular algorithm utilized for this purpose. This algorithm starts from one end-point of the line to the other end-point by calculating one point at each step. As a result, the calculation time for all the points depends on the length of the line thereby the number of the total points presented. In this paper, we developed an approach to speed up the Bresenham algorithm by partitioning each line into number of segments, find the points belong to those segments and drawing them simultaneously to formulate the main line. As a result, the higher number of segments generated, the faster the points are calculated. By employing 32 cores in the Field Programmable Gate Array, a line of length 992 points is formulated in 0.31μs only. The complete system is implemented using Zybo board that contains the Xilinx Zynq-7000 chip (Z-7010).<em></em></p>

scholarly journals Technology Mapping of FSM Oriented to LUT-Based FPGA

2020 ◽  
Vol 10 (11) ◽  
pp. 3926
Author(s):  
Marcin Kubica ◽  
Dariusz Kania
Keyword(s):  
Field Programmable Gate Array ◽  
Finite State Machine ◽  
Synthesis Method ◽  
Technology Mapping ◽  
Look Up Table ◽  
Finite State ◽  
Field Programmable ◽  
Simultaneous Synthesis ◽  
Transition Block ◽  
Logic Blocks

The main purpose of the paper is to present technology mapping of FSM (finite state machine) oriented to LUT (look-up table)-based FPGA (field-programmable gate array). The combinational part of an automaton, which consists of a transition block and an output block, was mapped in LUT-based logic blocks. In the paper, the idea of carrying out the combinational part of FSM was presented and leads to the reduction of the number of LUTs needed to carry out an automaton. The essence of this method is a simultaneous synthesis of the whole combinational block described in the form of multi-output function. The proposed idea makes it possible to conduct decomposition that may enable to share logic blocks, which can lead to the reduction of using resources of FPGA. The decomposition process was conducted using the analyzed DECOMP system. The effectiveness of the proposed idea of the FSM description was also confirmed by conducting decomposition with the usage of the ABC system. The obtained results prove the efficiency of the proposed synthesis method of FSM in comparison with the separate synthesis of a transition block and an output block.

scholarly journals Space-time trellis codes: Field programmable gate array approach

2020 ◽  
Vol 9 (3) ◽  
pp. 213
Author(s):  
Mallikarjuna Gowda C. P. ◽  
Raju Hajare
Keyword(s):  
Field Programmable Gate Array ◽  
High Speed ◽  
Low Cost ◽  
Digital Signal ◽  
Space Time ◽  
Trellis Codes ◽  
Software Environment ◽  
High Data ◽  
Field Programmable ◽  
Gate Array

This paper presents an implementation of Space-time Trellis Codes for 4-state on FPGA. To reach the very high data rates provided in STTC, a lot of expensive high-speed Digital Signal Processors (DSPs) should be employed for the real time applications, while it might not be affordable. This fact has motivated in designing dedicated hardware implementations using Field Programmable Gate Array (FPGA) with low cost and power consumption. The hardware device XC3S400, family Xilinx Spartan-3, and package PQ208 are used in this project, in which the STTC encoder and decoder utilizes maximum 10% and 22% as that of available device capacity respectively. The design has been simulated and synthesized successfully in Xilinx integrated software environment.

scholarly journals Enhancing Apple Maturation Recognition Performance Based on Field Programmable Gate Array Implementation

2019 ◽  
Vol 54 (6) ◽  
Author(s):  
Fouad H. Awad ◽  
Mohammed A. Fadhel ◽  
Khattab M. Ali Alheeti ◽  
Omran Al-Shamma ◽  
Laith Alzubaidi
Keyword(s):  
Parallel Processing ◽  
Field Programmable Gate Array ◽  
Recognition Performance ◽  
Recognition System ◽  
Clustering Technique ◽  
Field Programmable ◽  
Speed Up ◽  
Gate Array ◽  
Hardware Designs ◽  
Mature Apple

Recently, several techniques have been developed for vegetable and fruit maturing recognition. Adding hardware designs will enhance the recognition performance. Especially, parallel processing designs efficiently speed up the process functions. This paper utilizes a hardware parallel processing design called field programmable gate array for that purpose. In addition, two different methods; namely K-means clustering and color thresholding are used for recognizing the apple maturation. This study aims to design and implement a mature apple recognition system based on field programmable gate array. The results demonstrate that the color thresholding technique is faster, more reliable and more effective than the K-means clustering technique.

scholarly journals DWT Based Image Steganography with Seven Segment Display Pattern as a Key

2019 ◽  
Vol 8 (10S) ◽  
pp. 164-169 ◽  
Keyword(s):  
Field Programmable Gate Array ◽  
Image Steganography ◽  
Data Embedding ◽  
Secret Key ◽  
Novel Approach ◽  
Field Programmable ◽  
Speed Up ◽  
Gate Array ◽  
Reconfigurable Device

Steganography is one of the commanding and commonly used methods for embedding data. Realizing steganography in hardware supports to speed up steganography. This work realizesthe novel approach for generation of Key, for hiding and encoding processes of image steganography using LSB and HAAR DWT.The data embedding process is realized with seven segment display pattern as a secret key with various sizes using HAAR DWT and LSB. Maximum hiding effectiveness is also attained from this work. The same is implemented in hardware using reconfigurable device Field programmable gate array to improve the speed, area and power. The proposed work is also evaluated improved PSNR using MATLAB.

Field Programmable Gate Array Implementation for Highly Secured Palm Print Authentication

2020 ◽  
Vol 17 (9) ◽  
pp. 4565-4570
Author(s):  
Rajeev Shrivastava ◽  
Mohammad Javeed ◽  
G. Mallesham
Keyword(s):  
Field Programmable Gate Array ◽  
Wide Scope ◽  
After Effects ◽  
Low Level ◽  
High Speeds ◽  
Field Programmable ◽  
Speed Up ◽  
Transport Line ◽  
Palm Print ◽  
New Research

To guarantee individual ID and profoundly secure recognizable proof issues, biometric innovations will give more prominent security while improving precision. This new innovation has been done lately because of exchange misrepresentation, security breaks, individual ID, and so on. The excellence of biometric innovation is that it gives an exceptional code to every individual and can’t be duplicated or manufactured by others. So as to conquer the withdrawal of finger impression frameworks, this paper proposed a palm-based individual distinguishing proof framework, a promising and new research region in biometric recognizable proof frameworks in light of their uniqueness, adaptability and a quicker and wide scope of high speeds. It gives higher security on biometric unique mark frameworks with rich highlights, for example, wrinkles, constant brushes, mainlines, details focuses and single focuses. The fundamental motivation behind the proposed palm unique finger impression framework is to actualize a framework with higher exactness and speed up palm unique finger impression acknowledgment for some clients. Here, in this we presented an exceptionally ensured palm print recognizable proof framework with intrigue extraction territory (ROI) with a morphological procedure utilizing a two-way un-crushed or course vector (UDBW) change to separate low-level palm fingerprints enrolled capacities for its vector work (FV) and afterward after correlation is by estimating the separation between the palm transporters and the capacity of the palm and the capacity of the enlisted transport line and palm control. The after effects of the recreation show that the proposed biometric recognizable proof framework gives more noteworthy precision and solid distinguishing proof speed.

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