scholarly journals A CMOS W-Band Amplifier with Tunable Neutralization Using a Cross-Coupled MOS–varactor Pair

Electronics ◽  
2019 ◽  
Vol 8 (5) ◽  
pp. 537
Author(s):  
Byungho Yook ◽  
Kwangwon Park ◽  
Seungwon Park ◽  
Hyunkyu Lee ◽  
Taehoon Kim ◽  
...  
Keyword(s):  
High Gain ◽  
Common Source ◽  
Cmos Process ◽  
Capacitance Change ◽  
Chip Area ◽  
Dc Power ◽  
W Band ◽  
Stability Issue ◽  
Transistor Model ◽  
Mos Varactor

This paper presents a CMOS W-band amplifier adopting a novel neutralization technique for high gain and stability. The W-band amplifier consists of four common-source differential gain cells that are neutralized by a cross-coupled MOS–varactor pair. Contrary to conventional neutralizations, the proposed technique enables tunable neutralization, so that the gate-to-drain capacitance of transistors is accurately tracked and neutralized as the varactor voltage is adjusted. This makes the neutralization tolerant of capacitance change caused by process–voltage–temperature (PVT) variation or transistor model inaccuracy, which commonly occurs at mm-wave frequencies. The proposed tunable neutralization is experimentally confirmed by measuring gain and stability of the W-band amplifier fabricated in a 65-nm CMOS process. The amplifier achieves a measured gain of 17.5 dB at 79 GHz and a 3-dB bandwidth from 77.5 to 84 GHz without any stability issue. The DC power consumption is 56.7 mW and the chip area is 0.85 mm2.

scholarly journals Design and Analysis of a Novel 24 GHz Up-Conversion Mixer with Improved Derivative Super-Position Linearizer Technique for 5G Applications

Sensors ◽  
2021 ◽  
Vol 21 (18) ◽  
pp. 6118
Author(s):  
Abrar Siddique ◽  
Tahesin Samira Delwar ◽  
Prangyadarsini Behera ◽  
Manas Ranjan Biswal ◽  
Amir Haider ◽  
...  
Keyword(s):  
Noise Figure ◽  
High Gain ◽  
Common Source ◽  
Cmos Process ◽  
Third Order ◽  
Linear Coefficient ◽  
Chip Area ◽  
The Third ◽  
Fifth Generation ◽  
24 Ghz

A 24 GHz high linear, high-gain up-conversion mixer is realized for fifth-generation (5G) applications in the 65 nm CMOS process. The mixer’s linearity is increased by applying an Improved Derivative Super-Position (I-DS) technique cascaded between the mixer’s transconductance and switching stage. The high gain and stability of amplifiers in the transconductance stage of the mixer are achieved using novel tunable capacitive cross-coupled common source (TCC-CS) transistors. Using the I-DS, the third-order non-linear coefficient of current is closed to zero, enhancing the linearity. Additionally, a TCC-CS, which is realized by varactors, neutralizes the gate-to-drain parasitic capacitance (Cgd) of transistors in the transconductance stage of the mixer and contributes to the improvement of the gain and stability of the mixer. The measured 1 dB compression point OP1dB of the designed mixer is 4.1 dBm and IP1dB is 0.67 dBm at 24 GHz. The conversion gain of 4.1 dB at 24 GHz and 3.2 ± 0.9 dB, from 20 to 30 GHz is achieved in the designed mixer. Furthermore, a noise figure of 3.8 dB is noted at 24 GHz. The power consumption of the mixer is 4.9 mW at 1.2 V, while the chip area of the designed mixer is 0.4 mm2.

A Low Power High Gain CMOS LNA with Multiple-Feedback Network for Low Voltage UWB Receiver

2016 ◽  
Vol 25 (06) ◽  
pp. 1650051 ◽  
Author(s):  
Lv Zhao ◽  
Chunhua Wang
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Supply Voltage ◽  
High Gain ◽  
Low Noise ◽  
Common Source ◽  
Cmos Process ◽  
Chip Area ◽  
Feedback Network ◽  
Uwb Receiver

In this paper, a high gain low voltage low power Complementary Metal Oxide Semiconductor (CMOS) Low-noise Amplifier (LNA) using Chartered 0.18[Formula: see text][Formula: see text]m CMOS process for Ultra-wideband (UWB) receiver applications is presented. A novel multiple-feedback network constructed by the shunt feedback resistor with a transformer is adopted to realize desirable bandwidth extension and less chip area occupation in the common-source stage. All the cascaded transistors are configured by current-reuse structure and adjusted by forward body bias technique to further reduce supply voltage and power dissipation. The post-layout simulation results demonstrate that the proposed 3.4–10.1[Formula: see text]GHz UWB LNA accomplishes a maximum gain of 14.26[Formula: see text]dB with only 2.33[Formula: see text]mW power consumption at 0.8[Formula: see text]V supply voltage, while Noise Figure (NF) is 1.49–3.41[Formula: see text]dB and the chip area is 0.46[Formula: see text]mm2 including test pads (core area is 0.23[Formula: see text]mm2).

2.2–4.6-GHz Active Quasi-Circulator with > 24-dB Transmit–Receive Isolation

2019 ◽  
Vol 29 (05) ◽  
pp. 2050077
Author(s):  
Najam Muhammad Amin ◽  
Lianfeng Shen ◽  
Danish Kaleem ◽  
Zhi-Gong Wang ◽  
Keping Wang ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
The Body ◽  
Common Source ◽  
Cmos Process ◽  
Secondary Effects ◽  
Body Effect ◽  
Chip Area ◽  
Common Gate ◽  
Loading Effects ◽  
Better Than

An active quasi-circulator (AQC) integrated circuit is designed and fabricated in a 0.18-[Formula: see text]m CMOS process. The proposed design is based on a parallel combination of a common-source (CS) stage and a combined common-drain (CD) and common-gate (CG) topology. Scattering matrix of the core AQC circuit is derived considering MOSFET’s secondary effects, particularly the body effect as well as output loading effects. Measurements of the quasi-circulator reveal an insertion loss of [Formula: see text] dB between transmitter-to-antenna ports ([Formula: see text]) and of [Formula: see text] dB between antenna-to-receiver ports ([Formula: see text]), within a frequency band of 2.2–4.6 GHz. The isolation between the transmitter and the receiver ports ([Formula: see text]) is better than 24 dB with a maximum value of 29.5[Formula: see text]dB @ 3.6[Formula: see text]GHz. The power dissipation of the proposed AQC is 40[Formula: see text]mW and it covers an active chip area of 0.677[Formula: see text]mm2.

High Gain and Low Noise Single Balanced Wireless Receiver Front-End Circuit Design

2013 ◽  
Vol 284-287 ◽  
pp. 2647-2651
Author(s):  
Zhe Yang Huang ◽  
Che Cheng Huang ◽  
Jung Mao Lin ◽  
Chung Chih Hung
Keyword(s):  
Return Loss ◽  
Noise Figure ◽  
High Gain ◽  
Low Noise ◽  
Total Power ◽  
Cmos Process ◽  
Chip Area ◽  
Wireless Receiver ◽  
Front End ◽  
Total Power Consumption

This paper presents a wideband wireless receiver front-end for 3.1-5.0GHz band group-1 (BG-1) WiMedia application. The front-end circuits are designed in 0.18um standard CMOS process. The experimental results show the maximum conversion power gain is 45.5dB; minimum noise figure is 2.9dB. Input return loss is lower than -9.3dB and output return loss is lower than -6.8dB. The maximum LO conversion power is 0dBm. 3dB working frequency is 1.9GHz (3.1GHz-5.0GHz) Total power consumption is 24.3mW including LNA, mixer and all buffers. Total chip area is 1.27mm2 including dummy and pads.

A Low-Power, High-Gain, and Low-Noise 802.11a Down-Conversion Mixer in 0.35-μm SiGe Bi-CMOS Technology

2017 ◽  
Vol 26 (09) ◽  
pp. 1750134 ◽  
Author(s):  
Jun-Da Chen ◽  
Song-Hao Wang
Keyword(s):  
Low Power ◽  
Noise Figure ◽  
Supply Voltage ◽  
Cmos Technology ◽  
High Gain ◽  
Low Noise ◽  
Cmos Process ◽  
Conversion Gain ◽  
Dc Power ◽  
Down Conversion

The paper presents a novel 5.15[Formula: see text]GHz–5.825[Formula: see text]GHz SiGe Bi-CMOS down-conversion mixer for WLAN 802.11a receiver. The architecture used is based on Gilbert cell mixer, the combination of MOS transistors and HBT BJT transistor device characteristics. The hetero-junction bipolar transistor (HBT) topology is adopted at the transconductance stage to improve power gain and reduce noise factor, and the LO series-parallel CMOS switch topology will be applied to reduce supply voltage and dc power at the switching stage. This mixer is implemented in TSMC 0.35-[Formula: see text]m SiGe Bi-CMOS process, and the chip size including the test pads is 1.175*0.843[Formula: see text]mm2. The main advantages for the proposed mixer are high conversion gain, a moderate linearity, low noise figure, and low power. The post-simulation results achieved are as follows: 14[Formula: see text]dB power conversion gain, [Formula: see text]6[Formula: see text]dBm input third-order intercept point (IIP3), 6.85[Formula: see text]dB double side band (DSB) noise figure. The total mixer current is about 1.54[Formula: see text]mA from 1.4[Formula: see text]V supply voltage including output buffer. The total dc power consumption is 2.15[Formula: see text]mW.

scholarly journals A Low-Noise Amplifier Utilizing Current-Reuse Technique and Active Shunt Feedback for MedRadio Band Applications

2020 ◽  
pp. 306-316
Author(s):  
Mutanizam Abdul Mubin ◽  
◽  
Arjuna Marzuki
Keyword(s):  
Low Power ◽  
Return Loss ◽  
Noise Figure ◽  
High Gain ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Common Source ◽  
Cmos Process ◽  
Current Reuse ◽  
Noise Amplifier

In this work, a low-power 0.18-μm CMOS low-noise amplifier (LNA) for MedRadio applications has been designed and verified. Cadence IC5 software with Silterra’s C18G CMOS Process Design Kit were used for all design and simulation work. This LNA utilizes complementary common-source current-reuse topology and subthreshold biasing to achieve low-power operation with simultaneous high gain and low noise figure. An active shunt feedback circuit is used as input matching network to provide a suitable input return loss. For test and measurement purpose, an output buffer was designed and integrated with this LNA. Inductorless design approach of this LNA, together with the use of MOSCAPs as capacitors, help to minimize the die size. On post-layout simulations with LNA die area of 0.06 mm2 and simulated total DC power consumption of 0.5 mW, all targeted specifications are met. The simulated gain, input return loss and noise figure of this LNA are 16.3 dB, 10.1 dB and 4.9 dB respectively throughout the MedRadio frequency range. For linearity, the simulated input-referred P1dB of this LNA is -26.7 dBm while its simulated IIP3 is -18.6 dBm. Overall, the post-layout simulated performance of this proposed LNA is fairly comparable to some current state-of-the-art LNAs for MedRadio applications. The small die area of this proposed LNA is a significant improvement in comparison to those of the previously reported MedRadio LNAs.

Millimeter-wave dual-mode and dual-band switchable Gilbert up-conversion mixer in 65-nm CMOS process

2021 ◽  
pp. 1-5
Author(s):  
Fang Zhu ◽  
Guo Qing Luo
Keyword(s):  
Millimeter Wave ◽  
Complementary Metal Oxide Semiconductor ◽  
Local Oscillator ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Dual Band ◽  
Cmos Process ◽  
Pumping Power ◽  
Dual Mode ◽  
Dc Power

Abstract In this paper, a millimeter-wave (MMW) dual-mode and dual-band switchable Gilbert up-conversion mixer in a commercial 65-nm complementary metal oxide semiconductor (CMOS) process is presented. By simply changing the bias, the proposed CMOS Gilbert up-conversion mixer can be switched between subharmonic and fundamental operation modes for MMW dual-band applications. With a low local oscillator pumping power of 3 dBm and low dc power consumption of 6 mW, the proposed CMOS Gilbert up-conversion mixer exhibits a measured conversion gain of −0.5 ± 1.5 dB from 37 to 50 GHz and 2.5 ± 1.5 dB from 17.5 to 32 GHz for the subharmonic and fundamental modes, respectively.

Investigations of a high gain W-band gyro-TWA

2021 ◽  
Author(s):  
C. R. Donaldson ◽  
P. MacInnes ◽  
C. W. Robertson ◽  
L. Zhang ◽  
C. G. Whyte
Keyword(s):  
High Gain ◽  
W Band

scholarly journals A Sigma-Delta ADC for Signal Conditioning IC of Automotive Piezo-Resistive Pressure Sensors with over 80 dB SNR

Sensors ◽  
2018 ◽  
Vol 18 (12) ◽  
pp. 4199 ◽  
Author(s):  
Behnam Samadpoor Rikan ◽  
Sang-Yun Kim ◽  
Nabeel Ahmad ◽  
Hamed Abbasizadeh ◽  
Muhammad Riaz Ur Rehman ◽  
...  
Keyword(s):  
Input Signal ◽  
Flicker Noise ◽  
Signal To Noise Ratio ◽  
Pressure Sensors ◽  
High Gain ◽  
Cmos Process ◽  
Signal Conditioning ◽  
Sigma Delta ◽  
Cic Filter ◽  
Decimation Filter

This paper presents a second-order discrete-time Sigma-Delta (SD) Analog-to-Digital Converter (ADC) with over 80 dB Signal to Noise Ratio (SNR), which is applied in a signal conditioning IC for automotive piezo-resistive pressure sensors. To reduce the flicker noise of the structure, choppers are used in every stage of the high gain amplifiers. Besides, to reduce the required area and power, only the CIC filter structure is adopted as a decimation filter. This filter has a configurable structure that can be applied to different data rates and input signal bandwidths. The proposed ADC was fabricated and measured in a 0.18-µm CMOS process. Due to the application of only a CIC filter, the total active area of the SD-ADC and reference generator is 0.49 mm2 where the area of the decimation filter is only 0.075 mm2. For the input signal bandwidth of 1.22 kHz, it achieved over 80 dB SNR in a 2.5 MHz sampling frequency while consuming 646 µW power.

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