scholarly journals Open-Source Coprocessor for Integer Multiple Precision Arithmetic

Electronics ◽  
2020 ◽  
Vol 9 (7) ◽  
pp. 1141
Author(s):  
Kamil Rudnicki ◽  
Tomasz P. Stefański ◽  
Wojciech Żebrowski
Keyword(s):  
Open Source ◽  
Integrated Circuit ◽  
High Speed ◽  
Digital Circuit ◽  
Processing Unit ◽  
Single Chip ◽  
Integer Multiple ◽  
Central Processing ◽  
Multiple Precision ◽  
Multiple Precision Arithmetic

This paper presents an open-source digital circuit of the coprocessor for an integer multiple-precision arithmetic (MPA). The purpose of this coprocessor is to support a central processing unit (CPU) by offloading computations requiring integer precision higher than 32/64 bits. The coprocessor is developed using the very high speed integrated circuit hardware description language (VHDL) as an intellectual property (IP) core. Therefore, it can be implemented within field programmable gate arrays (FPGAs) at various scales, e.g., within a system on chip (SoC), combining CPU cores and FPGA within a single chip as well as FPGA acceleration cards. The coprocessor handles integer numbers with precisions in the range 64 bits–32 kbits, with the limb size set to 64 bits. In our solution, the sign-magnitude representation is used to increase the efficiency of the multiplication operation as well as to provide compatibility with existing software libraries for MPA. The coprocessor is benchmarked in factorial ( n ! ), exponentiation ( n n ) and discrete Green’s function (DGF) computations on Xilinx Zynq-7000 SoC on TySOM-1 board from Aldec. In all benchmarks, the coprocessor demonstrates better runtimes than a CPU core (ARM Cortex A9) executing the same computations using a software MPA library. For sufficiently large input parameters, our coprocessor is up to three times faster when implemented in FPGA on SoC, rising to a factor of ten in DGF computations. The open-source coprocessor code is licensed under the Mozilla Public License.

scholarly journals Ancient Vedic Multiplication Based Optimized High Speed Arithmetic Logic

2014 ◽  
Vol 3 (03) ◽  
pp. 01-06
Author(s):  
Mrs. Leena Rathi
Keyword(s):  
Integrated Circuit ◽  
High Speed ◽  
Research Work ◽  
Processing Unit ◽  
Central Processing ◽  
High Speeds ◽  
Quartus Ii ◽  
Hardware Description ◽  
Digital Processor ◽  
Very High

Here, we deal with most effective Vedic multiplication method dependent 4*4 bit arithmetic logic unit having high speed. In this paper, we will perform ALU operations. ALU is a development of research work that has been done for years so we have chosen this topic. Normally ALU is a heart of digital processor, central processing unit, microprocessor and micro controller. Every digital domain based technology has to depend on the performance of ALU. Hence, there is a necessity of ALU which generates high speeds which depends on the speed of multiplier. Therefore, we go for designing a 4-bit multiplier. To generate high speeds, multiplier is employed which is one of the important blocks of the hardware unit and also an important initiation of delay in the path. We have studied many algorithms for multiplication technique but research says that Vedic multiplication is most effective of all in terms of speed. The algorithm contains 16 sutra, out of which we are employing URDHVA TIRYAKBHYAM and the code is written in Very High Speed Integrated Circuit Hardware Description. Our supporting synthesizing and simulating tools are Xilinx ISE9.2i and model sim-altra6.3g-pi (Quartus II) respectively. At last, we will compare 4-bit ALU with 4-bit Array ALU.     

scholarly journals Line of Sight Correction of High-Speed Liquid Crystal Using Overdriving Technology

Electronics ◽  
2020 ◽  
Vol 9 (9) ◽  
pp. 1477
Author(s):  
Hongyang Guo ◽  
Qing Li ◽  
Yangjie Xu ◽  
Yongmei Huang ◽  
Shengping Du
Keyword(s):  
Liquid Crystal ◽  
Response Time ◽  
High Speed ◽  
Pulse Width Modulation ◽  
Response Speed ◽  
Line Of Sight ◽  
Processing Unit ◽  
Driving Voltage ◽  
Light Modulator ◽  
Central Processing

In the line of sight correction system, the response time of the liquid crystal spatial light modulator under the normal driving voltage is too long to affect system performance. On the issues, an overdriving method based on a Field-Programmable Gate Array (FPGA) is established. The principle of the overdrive is to use a higher voltage difference to achieve a faster response speed of liquid crystal. In this scheme, the overdriving look-up table is used to seek the response time of the quantized phase, and the liquid crystal electrode is driven by Pulse–Width Modulation (PWM). All the processes are performed in FPGA, which releases the central processing unit (CPU) memory and responds faster. Adequate simulations and experiments are introduced to demonstrate the proposed method. The overdriving experiment shows that the rising response time is reduced from 530 ms to 34 ms, and the falling time is from 360 ms to 38 ms under the overdriving voltage. Typical light tracks are imitated to evaluate the performance of the line of sight correction platform. Results show that using the overdrive the −3 dB rejection frequency was increased from 1.1 Hz to 2.6 Hz. The suppression ability of the overdrive is about −20 dB at 0.1 Hz, however the normal-driving suppression ability is only about −13 dB.

Area Efficient Carry Select Adder Using Negative Edge Triggered D-Flipflop

2014 ◽  
Vol 573 ◽  
pp. 187-193 ◽  
Author(s):  
Anitha Ponnusamy ◽  
Palaniappan Ramanathan
Keyword(s):  
Integrated Circuit ◽  
Power Dissipation ◽  
High Speed ◽  
Total Power ◽  
Single Chip ◽  
Flip Flop ◽  
Design And Optimization ◽  
Negative Edge ◽  
Carry Select Adder ◽  
Power Delay Product

The recent increase in popularity of portable systems and rapid growth of packaging density in VLSI circuit’s has enable designers to design complex functional units on a single chip. Power, area and speed plays a major role in the design and optimization of an integrated circuit. Carry select adder is high speed final stage adder widely used in many data processing units. In this work, conventional D-flip flop is replaced by a new design using negative edge triggered D-flip flop. The proposed CSA is implemented in a faster partitioned Dadda multiplier and simulated by using MICROWIND tool. The results reveal that for 16 bit CSA improvement of power delay product (PDP) of the proposed design using negative edge triggered D flip flop is 78% & 18% when compared to CSA with BEC and CSA with conventional D flip flop. When CSA implemented in a partitioned Dadda multiplier it results in performance improvement of 74 % with little increase in total power dissipation.

scholarly journals Method for improving ripple reduction during phase shedding in multiphase buck converters for SCADA systems

2021 ◽  
Vol 24 (1) ◽  
pp. 29
Author(s):  
Mini P. Varghese ◽  
A. Manjunatha ◽  
T. V. Snehaprabha
Keyword(s):  
Power Supply ◽  
Integrated Circuit ◽  
Buck Converter ◽  
Multiphase System ◽  
Processing Unit ◽  
Central Processing ◽  
Light Load ◽  
Field Programmable ◽  
Ripple Reduction ◽  
Application Specific Integrated Circuit

In the current digital environment, central processing unit (CPUs), field programmable gate array (FPGAs), application-specific integrated circuit (ASICs), as well as peripherals, are growing progressively complex. On motherboards in many areas of computing, from laptops and tablets to servers and Ethernet switches, multiphase phase buck regulators are seen to be more common nowadays, because of the higher power requirements. This study describes a four-stage buck converter with a phase shedding scheme that can be used to power processors in programmable logic controller (PLCs). The proposed power supply is designed to generate a regulated voltage with minimal ripple. Because of the suggested phase shedding method, this power supply also offers better light load efficiency. For this objective, a multiphase system with phase shedding is modeled in MATLAB SIMULINK, and the findings are validated.

A Novel Approach to Design a 4-Bit Binary Comparator Circuit with Reversible Logic using CDSM Gate

2015 ◽  
Vol 11 (1) ◽  
pp. 36-49
Author(s):  
Vandana Shukla ◽  
O. P. Singh ◽  
G. R. Mishra ◽  
R. K. Tiwari
Keyword(s):  
Low Power ◽  
Power Loss ◽  
Optical Computing ◽  
Logic Gates ◽  
Digital Circuit ◽  
Reversible Logic ◽  
Processing Unit ◽  
Quantum Cost ◽  
Central Processing ◽  
Control Circuits

In the recent scenario of microelectronic industry, the reversible logic is considered as the burgeonic technology for digital circuit designing. It deals with the aim to generate digital circuits with zero power loss characteristics. Optical computing, Nanotechnology, Low power CMOS design and Digital Signal Processing (DSP) processors are leading areas of development with the concept of reversible logic. Researchers have already proposed various subsystems of the computer for the creation of low power loss devices with the help of numerous available reversible logic gates. Here in this paper, the authors have proposed a new reversible gate named as CDSM gate with 4×4 size. This CDSM gate is used to design optimized 4-bit binary comparator. The optimization is improved as compared to the existing designs based on some significant performance parameters such as total number of gates, garbage outputs generated, constant inputs and quantum cost. Comparators are widely used in various computing applications such as counters, convertor, Central Processing Unit (CPU) and control circuits etc. The comparator circuits using reversible logic can be visualized as a low power loss subsystem for the development of improved digital systems.

A Hybrid Optimization Based on GPU Parallel Computing Method and its Application of Three Dimensional Large Eddy Simulations

2013 ◽  
Vol 275-277 ◽  
pp. 2589-2594 ◽  
Author(s):  
Yu Xuan Zhang ◽  
Song Ping Wu
Keyword(s):  
High Speed ◽  
Data Transfer ◽  
Three Dimensional ◽  
Processing Unit ◽  
Desktop Computer ◽  
Central Processing ◽  
Eddy Simulation ◽  
Turbulence Flow ◽  
Large Eddy ◽  
Optimization Schemes

Using compute Unified device architecture (CUDA), a traditional computational fluid dynamics (CFD) program is paralleled and optimized based on graphic processing unit (GPU). The calculation process is divided into two parts as serial and parallel. Their main characteristics are analyzed and different optimization schemes are given. CPU (central processing unit) and GPU work respectively as flow control and high-speed parallel computation. Bandwidth between devices is applied effectively. Data transfer between devices is moderately improved to simplify algorithm. Finally, the method is verified by simulating a three-dimensional isotropic homogeneous turbulence flow field. The calculation uses large eddy simulation (LES) method with secondary filter and solves the three-dimensional N-S equations. The maximum grid number achieves 8,000,000 and takes 33 seconds each step. All calculations are using ordinary single desktop computer, optimized acceleration ratio can reach 9.

Development of an Automotive Electric Window Control System Based on CAN Bus

2014 ◽  
Vol 602-605 ◽  
pp. 1240-1243 ◽  
Author(s):  
Xu Chen ◽  
Xiao Feng Yin ◽  
Qi Chang Yang ◽  
Han Lu
Keyword(s):  
Control System ◽  
System Reliability ◽  
Can Bus ◽  
Processing Unit ◽  
Application Layer ◽  
Single Chip ◽  
Control Software ◽  
Wiring Harness ◽  
Central Processing ◽  
System A

An electric window control system based on low-speed CAN bus has been developed to reduce the wiring harness of vehicle control system, improve the system reliability and cut overall costs. On the basis of requirement analysis of the control system, a CAN application layer communication protocol has been defined. The electric window control system has been designed using Freescale 16-bit single chip microprocessor MCS12DP256 as central processing unit, and the control software has also been developed, in which an integral algorithm was used to realize the anti-pinch function.

scholarly journals A Cost-Effective Solution to Improving the Electrical Performance of Metal Contacting Interfaces in IC System under Temperature-Humidity Environment

2019 ◽  
Vol 9 (19) ◽  
pp. 3950
Author(s):  
Li ◽  
Meng ◽  
Shi ◽  
Gao ◽  
Zhang ◽  
...  
Keyword(s):  
Contact Resistance ◽  
Integrated Circuit ◽  
System Reliability ◽  
Cost Effective ◽  
Electrical Performance ◽  
Processing Unit ◽  
Test Results ◽  
Effective Solution ◽  
Central Processing ◽  
Humidity Environment

Temperature-humidity (TH) induced failure mechanism (FM) of metal contacting interfaces in integrated circuit (IC) systems has played a significant role in system reliability issues. This paper focuses on central processing unit (CPU)/motherboard interfaces and studies several factors that are believed to have a great impact on TH performance. They include: Enabling load, surface finish quality, and contacting area. Test vehicles (TVs) of Clarkdale package and of Ibex peak motherboard were designed to measure low level contact resistance (LLCR) for catching any failure. Several sets of design of experiments (DOE) were conducted on 85°C/85% relative humidity and test results were analyzed. A proposal that correlates asperity spots and contact tip design with contact resistance was proposed and thus a cost-effective solution for improving electrical performance under TH was deduced. The proposal has proven to be reasonably effective in practice.

Sign in / Sign up

Export Citation Format

Share Document