Area Efficient Carry Select Adder Using Negative Edge Triggered D-Flipflop

2014 ◽  
Vol 573 ◽  
pp. 187-193 ◽  
Author(s):  
Anitha Ponnusamy ◽  
Palaniappan Ramanathan
Keyword(s):  
Integrated Circuit ◽  
Power Dissipation ◽  
High Speed ◽  
Total Power ◽  
Single Chip ◽  
Flip Flop ◽  
Design And Optimization ◽  
Negative Edge ◽  
Carry Select Adder ◽  
Power Delay Product

The recent increase in popularity of portable systems and rapid growth of packaging density in VLSI circuit’s has enable designers to design complex functional units on a single chip. Power, area and speed plays a major role in the design and optimization of an integrated circuit. Carry select adder is high speed final stage adder widely used in many data processing units. In this work, conventional D-flip flop is replaced by a new design using negative edge triggered D-flip flop. The proposed CSA is implemented in a faster partitioned Dadda multiplier and simulated by using MICROWIND tool. The results reveal that for 16 bit CSA improvement of power delay product (PDP) of the proposed design using negative edge triggered D flip flop is 78% & 18% when compared to CSA with BEC and CSA with conventional D flip flop. When CSA implemented in a partitioned Dadda multiplier it results in performance improvement of 74 % with little increase in total power dissipation.

Design of implicit pulsed-dual edge triggering flip flop for low power and high speed clocking systems

2019 ◽  
Vol 18 (01) ◽  
pp. 1941009
Author(s):  
P. Nagarajan ◽  
N. Ashok Kumar ◽  
P. Venkat Ramana
Keyword(s):  
Power Dissipation ◽  
High Speed ◽  
Power Saving ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Process Technology ◽  
Flip Flop ◽  
Energy Product ◽  
Power Delay Product ◽  
And Storage

The flip-flops are considered as major contributors to the power dissipation of the clocking system, which is made up of the clock provision network and storage elements (latches, flip-flops). The power- and delay-efficient new implicit-pulsed dual-edge triggering flip-flop circuit (IP-DETFF) is proposed with two latching stages by employing an implicit-pulse triggering, dual-edge clocking and reducing the number of clocked loads. This leads to the reduction of power consumption due to clock allocation tree (pclk-tree) and reduces the delay time. The dual-edge clocking technique is incorporated into this proposed design without an increment of the number of transistors and minimizes the operating frequency as half. This methodology is also employed in this proposed design to construct new latching part of the flip-flop circuit. The performance of proposed flip-flop is analyzed by simulating the circuit at 0.12[Formula: see text][Formula: see text]m CMOS (complementary metal oxide semiconductor) process technology. The simulation results show that the proposed design achieves power saving from 11.22% to 54.81%, improvement of speed from 67% to 71.50%, power-delay product (PDP) from 74.85% to 81.26 %, energy-delay product (EDP) from 87.86% to 92.4% and power-energy product (PEP) from 75.24% to 93.57% compared to the conventional flip-flops.

Performance Analysis of Various Multipliers Using 8T-full Adder with 180nm Technology

2020 ◽  
Vol 13 (6) ◽  
pp. 864-870
Author(s):  
Sai Venkatramana Prasada G.S ◽  
G. Seshikala ◽  
S. Niranjana
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
High Performance ◽  
Full Adder ◽  
Fundamental Operation ◽  
Wallace Tree ◽  
Power Delay Product ◽  
The Comparative Study ◽  
Wallace Tree Multiplier

Background: This paper presents the comparative study of power dissipation, delay and power delay product (PDP) of different full adders and multiplier designs. Methods: Full adder is the fundamental operation for any processors, DSP architectures and VLSI systems. Here ten different full adder structures were analyzed for their best performance using a Mentor Graphics tool with 180nm technology. Results: From the analysis result high performance full adder is extracted for further higher level designs. 8T full adder exhibits high speed, low power delay and low power delay product and hence it is considered to construct four different multiplier designs, such as Array multiplier, Baugh Wooley multiplier, Braun multiplier and Wallace Tree multiplier. These different structures of multipliers were designed using 8T full adder and simulated using Mentor Graphics tool in a constant W/L aspect ratio. Conclusion: From the analysis, it is concluded that Wallace Tree multiplier is the high speed multiplier but dissipates comparatively high power. Baugh Wooley multiplier dissipates less power but exhibits more time delay and low PDP.

A LOW-POWER AND HIGH-SPEED D FLIP-FLOP USING A SINGLE LATCH

2002 ◽  
Vol 11 (01) ◽  
pp. 51-55
Author(s):  
ROBERT C. CHANG ◽  
L.-C. HSU ◽  
M.-C. SUN
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
Operating Frequency ◽  
Flip Flop ◽  
Lower Power ◽  
Simulation Results ◽  
Hspice Simulation

A novel low-power and high-speed D flip-flop is presented in this letter. The flip-flop consists of a single low-power latch, which is controlled by a positive narrow pulse. Hence, fewer transistors are used and lower power consumption is achieved. HSPICE simulation results show that power dissipation of the proposed D flip-flop has been reduced up to 76%. The operating frequency of the flip-flop is also greatly increased.

Design and Implementation of QCA D-Flip-Flops and RAM Cell Using Majority Gates

2019 ◽  
Vol 28 (05) ◽  
pp. 1950079 ◽  
Author(s):  
Trailokya Nath Sasamal ◽  
Ashutosh Kumar Singh ◽  
Umesh Ghanekar
Keyword(s):  
Circuit Design ◽  
High Speed ◽  
High Performance ◽  
Single Layer ◽  
Memory Cell ◽  
Design Parameters ◽  
Flip Flop ◽  
Negative Edge ◽  
Wire Crossing ◽  
The Common

Quantum-dot cellular automata (QCA) is one of the promising technologies that enable nanoscale circuit design with high performance and low-power consumption features. As memory cell and flip-flops are rudimentary for most of the digital circuits, having a high speed, and a less complex memory cell is significantly important. This paper presents novel architecture of D flip-flops and memory cell using a recently proposed five-input majority gate in QCA technology and simulated by QCADesigner tool version 2.0.3. The simulation results show that the proposed D flip-flops and the memory cell are more superior to the existing designs by considering the common design parameters. The proposed RAM cell spreads over an area of 0.12[Formula: see text][Formula: see text]m2and delay of 1.5 clock cycles. The proposed level-triggered, positive/negative edge-triggered, and dual edge-triggered D flip-flop uses 14%, 33%, and 21% less area, whereas the latency is 40%, 27%, and 25% less when compared to the previous best design. In addition, all the proposed designs are implemented in a single layer QCA and do not require any single or multilayer wire crossing.

Various Logically Optimized D Flip Flop Circuits-A Comparative Study in Submicron Technology

2015 ◽  
Vol 4 (2) ◽  
Author(s):  
Abhijit Asthana ◽  
Shyam Akashe
Keyword(s):  
Comparative Study ◽  
Power Dissipation ◽  
Leakage Power ◽  
Simulation Test ◽  
Flip Flop ◽  
Chip Area ◽  
Low Leakage ◽  
Signal Systems ◽  
To Come ◽  
Power Delay Product

D-Flip Flop (D_FF) is a very important component of various digital, analog and mixed signal systems and designs. It is obvious to come up with optimized D_FF, that cater the needs of low leakage power, less power dissipation, less chip area on the chip and low delays. This paper presents a comparative study of various logically optimized circuits of D_FF using 8T, 11T, 12T and conventional 18T D_FF. The simulation, test circuits, schematics & layouts etc are done on Cadence Virtuoso tool in 180 nm technology. Designs are compared on grounds of power dissipation, leakage power, delays and power delay product.

scholarly journals Subthreshold Region based Linear Feedback Shift Register

2019 ◽  
Vol 8 (6S2) ◽  
pp. 817-821
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
System Level ◽  
Linear Feedback ◽  
Portable Devices ◽  
Subthreshold Region ◽  
Flip Flop ◽  
Ultra Low Power

Growing demand for portable devices and fast increases in complexity of chip cause power dissipation is an important parameter. Power consumption and dissipation or generations of more heat possess a restriction in the direction of the integration of more transistors. Several methods have been proposed to reduce power dissipation from system level to device level. Subthreshold circuits are widely used in more advanced applications due to ultra low-power consumption. The present work targets on construction of linear feedback shift registers (LFSR) in weak inversion region and their performance observed in terms of parameters like power delay product (PDP). In CMOS circuits subthreshold region of operation allows a low-power for ample utilizations but this advantage get with the penalty of flat speed. For the entrenched and high speed applications, improving the speed of subthreshold designs is essential. To enhance this, operate the devices at maximum current over capacitance. LFSR architectures build with various types of D flip flop and XOR gate circuits are analyzed. Circuit level Simulation is carried out using 130 nm technologies.

Design of low power and high speed implicit pulse flip-flop and its application

2018 ◽  
Vol 7 (3) ◽  
pp. 1893 ◽  
Author(s):  
Kuruvilla John ◽  
Vinod Kumar R S ◽  
Kumar S S
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
Product Performance ◽  
Power Performance ◽  
Flip Flop ◽  
Power Efficient ◽  
Pass Transistor ◽  
Simulation Results ◽  
Power Delay Product ◽  
Pmos Transistor

In this paper, a new power efficient and high speed pulsed-triggered flip-flop in implicit style with conditional pulse enhancement and signal feed-through (CPESFTFF) is proposed. This novel architecture is presented for the pulse-triggered D-FF in the CMOS 90-nm technology. Two important features are embedded in this flip-flop architecture. Firstly, a conditional enhancement in width and height of the triggering pulses by using an additional pMOS transistor in the structure is done. Secondly, a modified signal feed-through mechanism which directly samples the input to output by using an nMOS pass transistor is introduced. The proposed design achieves better speed and power performance by successfully solving the longest discharging path problem. The simulation results show that the proposed architecture has improvement in terms of power consumption, D-to-Q delay, and Power Delay Product Performance (PDP) in comparison with other conventional P-FF architectures. A 3-bit up counter is also implemented using proposed P-FF.  

SMALL-SCALE InGaP/GaAs HETEROJUNCTION BIPOLAR TRANSISTORS FOR HIGH-SPEED AND LOW-POWER INTEGRATED-CIRCUIT APPLICATIONS

2001 ◽  
Vol 11 (01) ◽  
pp. 115-136 ◽  
Author(s):  
TOHRU OKA ◽  
KOJI HIRATA ◽  
HIDEYUKI SUZUKI ◽  
KIYOSHI OUCHI ◽  
HIROYUKI UCHIYAMA ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Heterojunction Bipolar Transistors ◽  
Integrated Circuit ◽  
High Speed ◽  
Bipolar Transistors ◽  
Small Scale ◽  
Flip Flop ◽  
Base Electrode ◽  
Power Integrated Circuit

Small-scale InGaP/GaAs heterojunction bipolar transistors (HBTs) with high-speed as well as low-current operation are demonstrated. To reduce the emitter size SE and the base-collector capacitance CBC simultaneously, the HBTs are fabricated by using WSi/Ti as the base electrode and by burying SiO 2 in the extrinsic collector region. WSi/Ti metals simplify and facilitate processing to fabricate small base electrodes, and the buried SiO 2 reduces the parasitic CBC under the base electrode. The cutoff frequency fT of 156 GHz and the maximum oscillation frequency f max of 255 GHz were obtained at a collector current Ic of 3.5 mA for the HBT with SE of 0.5 μ m ×4.5 μ m , and fT of 114 GHz and f max of 230 GHz were obtained at IC of 0.9 mA for the HBT with SE of 0.25 μ m ×1.5 μ m . A 1/8 static frequency divider operated at a maximum toggle frequency of 39.5 GHz with a power consumption per flip-flop of 190 mW. A transimpedance amplifier provides a gain of 46.5 dB·Ω with a bandwidth of 41.6 GHz at a power consumption of 150 mW. These results indicate the great potential of our HBTs for high-speed. low power integrated circuit applications.

VLSI Implementation of High Speed Energy-Efficient Truncated Multiplier

2018 ◽  
Vol 27 (05) ◽  
pp. 1850077 ◽  
Author(s):  
K. N. Vijeyakumar ◽  
S. Elango ◽  
S. Kalaiselvi
Keyword(s):  
Power Dissipation ◽  
Energy Efficient ◽  
High Speed ◽  
Total Error ◽  
Absolute Error ◽  
Structural Level ◽  
Chip Area ◽  
Vedic Mathematics ◽  
Power Delay Product ◽  
Compiler Performance

In this brief, we present the design and evaluation of a high speed and energy-efficient truncated multiplier for unsigned multiplication, such that the average absolute error due to truncation and rounding is kept minimal. The proposed algorithm eliminates a few least significant Partial Product (PP) bits and adds correction bias at appropriate PP bit positions to minimize the total error. From the literatures reviewed, it is clear that there is scope for reducing delay in multiplication using sutras of ancient vedic mathematics. This work uses a simple “crosswise and vertical sutra” of Vedic mathematics to generate PP bits. The proposed methodology groups the input into [Formula: see text]/2 bits, eliminates least subgroup multiplication ([Formula: see text]) and deletes few least significant bits in other subgroup multiplications to reduce area and power dissipation. In addition, correction biase are added at appropriate bit positions to reduce the overall absolute error due to the elimination of few PP bits and rounding of final product. Experimental evaluation of the proposed truncated design is carried out through structural level VHDL modeling and simulations using Synopsys design compiler. Performance analysis revealed Chip-Area Ratio (CAR%) to be 33.81% and Power-Delay Product (PDP) of 14.84[Formula: see text]pJ of proposed truncated design for an [Formula: see text] multiplication.

scholarly journals DESIGN APPROACHES FOR LOW POWER- LOW AREA D FLIP FLOP S IN NANO TECHNOLOGY

2013 ◽  
pp. 231-236
Author(s):  
FAYAZ KHAN ◽  
SIREESH BABU
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Vital Role ◽  
Leakage Power ◽  
Total Power ◽  
Short Channel ◽  
Qualitative Comparison ◽  
Flip Flop ◽  
Low Area ◽  
Total Power Consumption

This paper enumerates design of D flip flop with low power and low area for low power applications, for that analysis of various D-flip flops for low power dissipation ,area and delays is carried out at 0.12um to achieve low power, low-area the technology is scaled down to nanometer ranges, due to shrinking process, the leakage power tends to play a vital role in total power consumption at nano meter technology. In this paper, different D flip flop circuits are designed using Berkeley Short Channel Insulated Gate MOSFET (BSIM4) model equations., in this paper to reduce leakage power at 90nm 70nm and 50nm we implement leakage power reduction techniques six techniques are considered they are namely Sleep transistor, sleepy stack, Dual sleep ,Dual stack Forced Transistor sleep (FTS) and Sleepy keeper From the results, it is observed that SLEEP TRANSISTOR, and SLEEPY KEEPER.FORCED TRANSISTOR SLEEP techniques produces lower power dissipation than the other techniques , in this paper a qualitative comparison is done with the help of Dsch,, Micro wind Simulation tools, this paper concludes that a leakage reduction technique produce different power optimization levels for different architectures and employing a suitable technique for a particular architecture will be an effective way of reducing the leakage current and thereby static power.

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