A 93.4% Efficiency 8-mV Offset Voltage Constant On-Time Buck Converter With an Offset Cancellation Technique

2020 ◽  
Vol 67 (10) ◽  
pp. 2069-2073
Author(s):  
Robert Chen-Hao Chang ◽  
Wei-Chih Chen ◽  
Jerry Kuei-Shou Huang
Keyword(s):  
Buck Converter ◽  
Offset Cancellation ◽  
Offset Voltage

scholarly journals Robust Offset-Cancellation Sense Amplifier for an Offset-Canceling Dual-Stage Sensing Circuit in Resistive Nonvolatile Memories

Electronics ◽  
2020 ◽  
Vol 9 (9) ◽  
pp. 1403 ◽  
Author(s):  
Taehui Na
Keyword(s):  
Supply Voltage ◽  
Dead Zone ◽  
Technology Scaling ◽  
Offset Cancellation ◽  
Sense Amplifier ◽  
Offset Voltage ◽  
Area Overhead ◽  
Nonvolatile Memories ◽  
Dual Stage ◽  
The Cost

With technology scaling, achieving a target read yield of resistive nonvolatile memories becomes more difficult due to increased process variation and decreased supply voltage. Recently, an offset-canceling dual-stage sensing circuit (OCDS-SC) has been proposed to improve the read yield by canceling the offset voltage and utilizing a double-sensing-margin structure. In this paper, an offset-canceling zero-sensing-dead-zone sense amplifier (OCZS-SA) combined with the OCDS-SC is proposed to significantly improve the read yield. The OCZS-SA has two major advantages, namely, offset voltage cancellation and a zero sensing dead zone. The Monte Carlo HSPICE simulation results using a 65-nm predictive technology model show that the OCZS-SA achieves 2.1 times smaller offset voltage with a zero sensing dead zone than the conventional latch-type SAs at the cost of an increased area overhead of 1.0% for a subarray size of 128 × 16.

scholarly journals Dynamic Offset Compensated Operational Amplifiers

2021 ◽  
Author(s):  
Ara Abdulsatar Assim Assim ◽  
Evgenii Balashov
Keyword(s):  
Dynamic Range ◽  
Flicker Noise ◽  
Input Voltage ◽  
High Gain ◽  
Operational Amplifiers ◽  
Analog To Digital ◽  
Offset Cancellation ◽  
Offset Voltage ◽  
Low Offset ◽  
The Given

The given work is devoted to designing and implementing different dynamic offset cancellation techniques for 50 nm technology CMOS operational amplifiers. The goal is to minimize or get rid of the effects of the offset voltage. Offset voltage exists in all differential amplifiers due to the fact that no pair of transistors can be fabricated with the same size, there is always a slight difference in their dimensions (length or width), this gives rise to an undesirable effect called offset, the value of offset voltage for cheap commercial amplifiers are in the range of 1 to 10 mV, de-spite the fact that this isn’t a significant value, due to the high gain of such amplifiers, this voltage is amplified by tens or hundreds of times, this results in clipping of the output signal and this further limits the amplifier’s maximum allowable input voltage within the given dynamic range, hence its of great importance to take this small voltage into consideration, low-offset amplifiers find applications in mixers, analog to digital converters, instrumentation devices, etc. In this thesis, by using two different techniques for removing offset voltage (chopping and auto-zeroing), five low offset operational amplifiers were designed. The implemented methods reduced the flicker noise by more than 457 times (from 9.4 nV/√Hz to 20 pV/√Hz) at 1 Hz. All the simulations were done using Cadence Virtuoso.

Pseudo-Ramp Current Balance (PRCB) Technique With Offset Cancellation Control (OCC) in Dual-Phase DC-DC Buck Converter

2014 ◽  
Vol 22 (10) ◽  
pp. 2192-2205 ◽  
Author(s):  
Yi-Ping Su ◽  
Wei-Chung Chen ◽  
Yu-Ping Huang ◽  
Yu-Huei Lee ◽  
Ke-Horng Chen ◽  
...  
Keyword(s):  
Buck Converter ◽  
Dual Phase ◽  
Offset Cancellation

scholarly journals A Pseudo-Constant Frequency Constant On-Time Buck Converter With Internal Current Ripple Injection and Output DC Offset Cancellation

IEEE Access ◽  
2019 ◽  
Vol 7 ◽  
pp. 175443-175453 ◽  
Author(s):  
Quan Sun ◽  
Yanzhao Ma ◽  
Zhengjie Ye ◽  
Xiaofei Wang ◽  
Hong Zhang
Keyword(s):  
Buck Converter ◽  
Constant Frequency ◽  
Offset Cancellation ◽  
Dc Offset ◽  
Current Ripple

A LOW OFFSET HIGH SPEED COMPARATOR FOR PIPELINE ADC

2013 ◽  
Vol 22 (04) ◽  
pp. 1350018 ◽  
Author(s):  
ZHANGMING ZHU ◽  
HONGBING WU ◽  
GUANGWEN YU ◽  
YANHONG LI ◽  
LIANXI LIU ◽  
...  
Keyword(s):  
Monte Carlo Simulation ◽  
Power Dissipation ◽  
High Speed ◽  
Cmos Process ◽  
Pipeline Adc ◽  
Analog To Digital ◽  
Offset Cancellation ◽  
Reduction Techniques ◽  
Offset Voltage ◽  
Low Offset

A low offset and high speed preamplifier latch comparator is proposed for high-speed pipeline analog-to-digital converters (ADCs). In order to realize low offset, both offset cancellation techniques and kickback noise reduction techniques are adopted. Based on TSMC 0.18 μm 3.3 V CMOS process, Monte Carlo simulation shows that the comparator has a low offset voltage 1.1806 mV at 1 sigma at 125 MHz, with a power dissipation of 413.48 μW.

scholarly journals A 40 MHz 70 dB Gain Variable Gain Amplifier Design Using the gm/ID Design Method

2009 ◽  
Vol 4 (1) ◽  
pp. 7-12
Author(s):  
Fernando Paixão Cortes ◽  
Sergio Bampi
Keyword(s):  
Design Method ◽  
Gain Control ◽  
Variable Gain Amplifier ◽  
Cmos Process ◽  
Offset Cancellation ◽  
Variable Gain ◽  
Offset Voltage ◽  
Amplifier Design ◽  
Time Offset ◽  
Bond Pads

This paper addresses the design and post-fabrication measurements of a 40 MHz CMOS Variable Gain Amplifier (VGA) with a 0 to 70 dB gain control range, using the gm/ID design methodology. The VGA architecture is based on a differential pair stage with an automatic continuous-time offset cancellation circuitry, providing an input offset voltage tolerance up to 50 mV. The 3-stage VGA was designed and fabricated through MOSIS service in an IBM 0.18 μm CMOS process. The VGA dissipates 2.6 mA from a 1.8 V supply, with 34,840 μm2 circuit area, excluding bond-pads.

scholarly journals DRIVER OUTPUT IMPEDANCE CALIBRATION SYSTEM WITH COMPARATOR UNIT OFFSET CANCELLATION

2021 ◽  
Vol 55 (1 (254)) ◽  
pp. 81-89
Author(s):  
Vazgen S. Gevorgyan
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Channel Length ◽  
Fine Tuning ◽  
Reference Frequency ◽  
Output Impedance ◽  
Noise Sources ◽  
Digital To Analog Converter ◽  
Offset Cancellation ◽  
Offset Voltage

In modern integrated circuits, the channel length of the transistors is reduced, and the supply voltages are also reduced. But the threshold voltages of the transistors cannot be reduced so quickly due to the physical properties of the materials used, which decreases the operating range of the transistors and makes noises comparable to them. Therefore, it is necessary to eliminate the influence of noise sources in the circuits, in particular, reflections between the transmission line and the output of the transmitter. A system is proposed for calibrating the output impedance of the transmitter based on an accurate external resistor with comparator unit offset voltage compensation. Existing analog and reference frequency based solutions have key disadvantages such as the inability to compensate the offset voltage after the integrated circuit is fabricated, and the distribution of the calibration voltage across the Input/Output device and constant power consumption during the operation. The proposed circuit includes a high-precision digital-to-analog converter to compensate the comparator offset voltage. It generates calibration codes for the pull-up and pull-down parts of the transmitter output buffer, and provides fine tuning of the output impedance. The circuit was modeled using 16 nm FinFET process elements and simulated with HSPICE simulator.

scholarly journals Dynamic Offset Compensated Operational Amplifiers

2021 ◽  
Author(s):  
Ara Abdulsatar Assim Assim ◽  
Evgenii Balashov
Keyword(s):  
Dynamic Range ◽  
Flicker Noise ◽  
Input Voltage ◽  
High Gain ◽  
Operational Amplifiers ◽  
Analog To Digital ◽  
Offset Cancellation ◽  
Offset Voltage ◽  
Low Offset ◽  
The Given

The given work is devoted to designing and implementing different dynamic offset cancellation techniques for 50 nm technology CMOS operational amplifiers. The goal is to minimize or get rid of the effects of the offset voltage. Offset voltage exists in all differential amplifiers due to the fact that no pair of transistors can be fabricated with the same size, there is always a slight difference in their dimensions (length or width), this gives rise to an undesirable effect called offset, the value of offset voltage for cheap commercial amplifiers are in the range of 1 to 10 mV, de-spite the fact that this isn’t a significant value, due to the high gain of such amplifiers, this voltage is amplified by tens or hundreds of times, this results in clipping of the output signal and this further limits the amplifier’s maximum allowable input voltage within the given dynamic range, hence its of great importance to take this small voltage into consideration, low-offset amplifiers find applications in mixers, analog to digital converters, instrumentation devices, etc. In this thesis, by using two different techniques for removing offset voltage (chopping and auto-zeroing), five low offset operational amplifiers were designed. The implemented methods reduced the flicker noise by more than 457 times (from 9.4 nV/√Hz to 20 pV/√Hz) at 1 Hz. All the simulations were done using Cadence Virtuoso.

Sign in / Sign up

Export Citation Format

Share Document