scholarly journals A Two-Stage X-Band 20.7-dBm Power Amplifier in 40-nm CMOS Technology

Electronics ◽  
2020 ◽  
Vol 9 (12) ◽  
pp. 2198
Author(s):  
Zhichao Li ◽  
Shiheng Yang ◽  
Samuel B. S. Lee ◽  
Kiat Seng Yeo
Keyword(s):  
Output Power ◽  
Effective Conductivity ◽  
Building Blocks ◽  
Cmos Technology ◽  
Center Frequency ◽  
Cmos Process ◽  
Two Stage ◽  
Power Added Efficiency ◽  
X Band ◽  
Compact Size

For higher integration density, X-band power amplifiers (PAs) with CMOS technology have been widely discussed in recent publications. However, with reduced power supply voltage and device size, it is a great challenge to design a compact PA with high output power and power-added efficiency (PAE). In the proposed design, a 40-nm standard CMOS process is used for higher integration with other RF building blocks, compared with other CMOS PA designs with larger process node. Transistor cells are designed with neutralization capacitors to increase stability and gain performance of the PA. As a trade-off among gain, output power, and PAE, the transistor cells in driving stage and power stage are biased for class A and class AB operation, respectively. Both transistor cells consist of two transistors working in differential mode. Furthermore, transformer-based matching networks (TMNs) are used to realize a two-stage X-band CMOS PA with compact size. The PA achieves an effective conductivity (EC) of 117.5, which is among the highest in recently reported X-band PAs in CMOS technology. The PA also attains a saturated output power (Psat) of 20.7 dBm, a peak PAE of 22.4%, and a gain of 25.6 dB at the center frequency of 10 GHz under a 1 V supply in 40-nm CMOS.

Power performance of 65 nm CMOS integrated LDMOS transistors at WLAN and X-band frequencies

2015 ◽  
Vol 8 (2) ◽  
pp. 135-141
Author(s):  
Sara Lotfi ◽  
Olof Bengtsson ◽  
Jörgen Olsson
Keyword(s):  
Metal Oxide ◽  
Power Density ◽  
Output Power ◽  
Supply Voltage ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Area Network ◽  
Power Added Efficiency ◽  
X Band

Laterally diffused metal oxide semiconductor (LDMOS) transistors with 10 V breakdown voltage have been implemented in a 65 nm Complementary metal oxide semiconductor (CMOS) process without extra masks or process steps. Radio frequency (RF) performance for Wireless local area network (WLAN) frequencies and in X-band at 8 GHz is investigated by load-pull measurements in class AB operation for both 3.3 and 5 V supply voltage. Results at 2.45 GHz showed 290 mW/mm output power density with 17 dB linear gain and over 45% power added efficiency (PAE) at 4 dB compression at a supply voltage of 5 V. Furthermore, results in X-band at 8 GHz show 8 dB linear gain, 320 mW/mm output power density and over 22% PAE at 4 dB compression. Third-order intermodulation measurements at 8 GHz revealed OIP3 of 18.9 and 21.9 dBm at 3.3 and 5 V, respectively. The transistors were also tested for reliability which showed no drift in quiescent current after 26 h of DC stress while high-power RF stress showed only small extrapolated drift at 10 years in output power density. This is to the authors' knowledge the first time high output power density in X-band is demonstrated for integrated LDMOS transistors manufactured in a 65 nm CMOS process without extra process steps.

scholarly journals A 350-GHz Coupled Stack Oscillator with −0.8 dBm Output Power in 65-nm Bulk CMOS Process

Electronics ◽  
2020 ◽  
Vol 9 (8) ◽  
pp. 1214
Author(s):  
Thanh Dat Nguyen ◽  
Jong-Phil Hong
Keyword(s):  
Output Power ◽  
Supply Voltage ◽  
Second Harmonic ◽  
Power Level ◽  
Cmos Technology ◽  
Negative Resistance ◽  
Output Power Level ◽  
Cmos Process ◽  
Frequency Selective ◽  
Oscillation Frequencies

This paper presents a push-push coupled stack oscillator that achieves a high output power level at terahertz (THz) wave frequency. The proposed stack oscillator core adopts a frequency selective negative resistance topology to improve negative transconductance at the fundamental frequency and a transformer connected between gate and drain terminals of cross pair transistors to minimize the power loss at the second harmonic frequency. Next, the phases and the oscillation frequencies between the oscillator cores are locked by employing an inductor of frequency selective negative resistance topology. The proposed topology was implemented in a 65-nm bulk CMOS technology. The highest measured output power is −0.8 dBm at 353.2 GHz while dissipating 205 mW from a 2.8 V supply voltage.

Compact dual mode X-band SIW bandpass filter with wide spurious suppression using split square ring slot resonator

Circuit World ◽  
2020 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Sandhya Ramalingam ◽  
Umma Habiba Hyder Ali ◽  
Sharmeela Chenniappan
Keyword(s):  
Bandpass Filter ◽  
Equivalent Circuit Model ◽  
Circuit Board ◽  
Center Frequency ◽  
Design System ◽  
Dual Mode ◽  
Content Type ◽  
X Band ◽  
Compact Size ◽  
Spurious Suppression

Purpose This paper aims to design a dual mode X-band substrate integrated waveguide (SIW) bandpass filter in the conventional SIW structure. A pair of back-to-back square and split ring resonator is introduced in the single-layer SIW bandpass filter. The various coupling configurations of SIW bandpass filter using split square ring slot resonator is designed to obtain dual resonant mode in the passband. It is shown that the measured results agree with the simulated results to meet compact size, lower the transmission coefficient, better reflection coefficient, sharp sideband rejection and minimal group delay. Design/methodology/approach A spurious suppression of wideband response is suppressed using an open stub in the transmission line. The width and length of the stub are tuned to suppress the wideband spurs in the stopband. The measured 3 dB bandwidth is from 8.76 to 14.24 GHz with a fractional bandwidth of 48.04% at a center frequency of 11.63 GHz, 12.59 GHz. The structure is analyzed using the equivalent circuit model, and the simulated analysis is based on an advanced design system software. Findings This paper discusses the characteristics of resonator below the waveguide cut-off frequency with their working principles and applications. Considering the difficulties in combining the resonators with a metallic waveguide, a new guided wave structure – the SIW is designed, which is synthesized on a planar substrate with linear periodic arrays of metallized via based on the printed circuit board. Originality/value This study has investigated the wave propagation problem of the SIW loaded by square ring slot-loaded resonator. The electric dipole nature of the resonator has been used to achieve a forward passband in a waveguide environment. The proposed filters have numerous advantages such as high-quality factor, low insertion loss, easy to integrate with the other planar circuits and, most importantly, compact size.

scholarly journals An X-Band CMOS Digital Phased Array Radar from Hardware to Software

Sensors ◽  
2021 ◽  
Vol 21 (21) ◽  
pp. 7382
Author(s):  
Yue-Ming Wu ◽  
Hao-Chung Chou ◽  
Cheng-Yung Ke ◽  
Chien-Cheng Wang ◽  
Chien-Te Li ◽  
...  
Keyword(s):  
Phased Array ◽  
Beam Steering ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Injection Technique ◽  
Element Level ◽  
Digital Beamforming ◽  
Phased Array Radar ◽  
X Band ◽  
Compact Size

Phased array technology features rapid and directional scanning and has become a promising approach for remote sensing and wireless communication. In addition, element-level digitization has increased the feasibility of complicated signal processing and simultaneous multi-beamforming processes. However, the high cost and bulky characteristics of beam-steering systems have prevented their extensive application. In this paper, an X-band element-level digital phased array radar utilizing fully integrated complementary metal-oxide-semiconductor (CMOS) transceivers is proposed for achieving a low-cost and compact-size digital beamforming system. An 8–10 GHz transceiver system-on-chip (SoC) fabricated in 65 nm CMOS technology offers baseband filtering, frequency translation, and global clock synchronization through the proposed periodic pulse injection technique. A 16-element subarray module with an SoC integration, antenna-in-package, and tile array configuration achieves digital beamforming, back-end computing, and dc–dc conversion with a size of 317 ×149 × 74.6 mm3. A radar demonstrator with scalable subarray modules simultaneously realizes range sensing and azimuth recognition for pulsed radar configurations. Captured by the suggested software-defined pulsed radar, a complete range–azimuth figure with a 1 km maximum observation range can be displayed within 150 ms under the current implementation.

A 2.4-GHz 0.18μm Full-CMOS Single-Stage Class-E Power Amplifier With Temperature Effect for ISM Band Wireless Communication

2007 ◽  
Author(s):  
Mu-Chun Wang ◽  
Zhen-Ying Hsieh ◽  
Chieu-Ying Hsu ◽  
Shuang-Yuan Chen ◽  
Heng-Sheng Huang
Keyword(s):  
Temperature Effect ◽  
Output Power ◽  
Power Amplifier ◽  
Single Stage ◽  
Design System ◽  
Cmos Process ◽  
Power Added Efficiency ◽  
Ism Band ◽  
Stage Class ◽  
Class E

In this paper, we present a single-stage class-E power amplifier with multiple-gated shape as well as 0.18μm complementary metal-oxide-semiconductor (CMOS) process for 2.4GHz Industry-Science-Medicine (ISM) band. This power amplifier is able to be easily integrated into the system-on-chip (SoC) circuit. For the competition of lower cost and high integration in marketing concern, CMOS technology is fundamentally better than GaAs technology. We adopt the Advanced Design System software in circuit simulation coming from Agilent Company through the Chip Implementation Center (CIC) channel plus TSMC 0.18 μm device models. The simulation results with temperature effect, show the good performance such as an output power achievement of +22dBm under a 1.8V supply voltage; the power-added efficiency (PAE) is over 30%; the output impedance (S22) and the input impedance (S11) are fully lower than −15dB; the power gain (S21) is +11dB; the inverse isolation (S12) is below −26dB. This amplifier reaches its 1-dB compression point at an output level of 16.5dBm related to the input power 6.5dBm position. The output power with temperature variation from 0°C to 125°C depicts an acceptable spec. range, too.

A multilayer substrate integrated filter using dual dielectric modes

2019 ◽  
Vol 11 (08) ◽  
pp. 787-791
Author(s):  
Xiao-Xiao Yuan ◽  
Li-Heng Zhou ◽  
Jian-Xin Chen
Keyword(s):  
Printed Circuit Boards ◽  
Filter Design ◽  
Center Frequency ◽  
Circuit Boards ◽  
Dual Mode ◽  
X Band ◽  
Compact Size ◽  
Unloaded Quality Factor ◽  
Multilayer Substrate ◽  
Good Agreement

AbstractIn this paper, a novel multilayer substrate integrated dual-mode dielectric resonator (DR) filter is proposed. The square dual-mode DR is made of the high permittivity substrate by removing the undesired portions and the surface coppers so that the relatively high unloaded quality factor of the dominate TM11 pair can be obtained which compared to these fully dielectric-filled substrate integrated waveguides. Meanwhile, it can be easily integrated in an equivalent cavity implemented by multilayer printed circuit boards for filter design, showcasing low in-band loss, light weight, and compact size. For demonstration, a multilayer substrate integrated DR bandpass filter centered at X-band is designed and measured. Good agreement between the simulated and measured results can be observed, and the measured insertion loss at the passband center frequency (8.38 GHz) is 1.1 dB.

scholarly journals Analysis and Compensation of the AM-AM and AM-PM Distortion for CMOS Cascode Class-E Power Amplifier

2009 ◽  
Vol 2009 ◽  
pp. 1-9 ◽  
Author(s):  
Wen An Tsou ◽  
Wen Shen Wuen ◽  
Tzu Yi Yang ◽  
Kuei Ann Wen
Keyword(s):  
Output Power ◽  
Power Amplifier ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Signal Source ◽  
Nonlinear Capacitance ◽  
Power Added Efficiency ◽  
Equivalent Impedance ◽  
Common Gate ◽  
Class E

Analysis and compensation methodology of the AM-AM and AM-PM distortion of cascode class-E power amplifiers are presented. A physical-based model is proposed to illustrate that the nonlinear capacitance and transconductance cause the AM-AM and AM-PM distortion when modulating the supply voltage of the PA. A novel methodology that can reduce the distortion is also proposed. By degenerating common-gate transistor into a resistor, the constant equivalent impedance is obtained so that the AM-AM and AM-PM distortion is compensated. An experimental prototype of 2.6 GHz cascode class-E power amplifier with the AM-AM and AM-PM compensation has been integrated in a 0.18 μm CMOS technology, occupies a total die area of 1.6 mm2. It achieves a drain efficiency of 17.8% and a power-added efficiency of 16.6% while delivering 12 dBm of linear output power and drawing 31 mA from a 1.8 V supply. Finally, a co-simulation result demonstrated that, when the distortion of the PA has been compensated, the EVM is improved from −17 dB to −19 dB with an IEEE802.11a-like signal source.

A 60 GHz 14 dBm power amplifier with a transformer-based power combiner in 65 nm CMOS

2011 ◽  
Vol 3 (2) ◽  
pp. 99-105 ◽  
Author(s):  
Dixian Zhao ◽  
Ying He ◽  
Lianming Li ◽  
Dieter Joos ◽  
Wim Philibert ◽  
...  
Keyword(s):  
Output Power ◽  
Power Amplifier ◽  
Peak Power ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
60 Ghz ◽  
Power Combiner ◽  
Power Added Efficiency ◽  
Saturated Output Power

A 52–61 GHz power amplifier (PA) is implemented in 65 nm bulk complementary metal oxide semiconductor (CMOS) technology. The proposed PA employs a transformer-based power combiner to sum the output power from two unit PAs. Each unit PA uses transformer-coupled two-stage differential cascode topology. The differential cascode PA is able to increase the output power and ensure stability. The transformer-based passives enable a compact layout with the PA core area of only 0.3 mm2. The PA achieves a peak power gain of 10.2 dB with 3-dB bandwidth of 9 GHz. The measured saturated output power is 14.8 dBm with a peak power-added efficiency (PAE) of 7.2%. The reverse isolation is smaller than −33 dB from 25 to 65 GHz. The PA consumes a quiescent current of 143 mA from a 1.6 V supply.

scholarly journals A 28GHz Power Amplifier with Analog Predistortion Linearizer in 65nm CMOS

2021 ◽  
Vol 5 (2) ◽  
pp. 5-10
Author(s):  
He Peng ◽  
Yuqing Dou
Keyword(s):  
Output Power ◽  
Power Amplifier ◽  
Supply Voltage ◽  
Linearization Method ◽  
Cmos Process ◽  
Power Added Efficiency ◽  
Saturated Output Power ◽  
Gain Compensation ◽  
Predistortion Linearization ◽  
Frequency Power

This paper proposes that a radio frequency power amplifier is suitable for a 5G millimeter wave. It adopts a three-stage single-ended structure at 28GHz. An analog predistortion linearization method is used to improve the linearity of the power amplifier (PA). As a result, there is a significant improvement in power-added efficiency (PAE) and linearity is achieved. The Ka-band PA is implemented in TSMC 65nm CMOS process. At 1.2V supply voltage, the PA proposed in this paper achieves a saturated output power of 15.9dBm and a PAE of 16%. After linearization, the output power at the 1dB compression point is increased by 2dBm, with efficient gain compensation performance.

High power density SiGe millimeter-wave power amplifiers

2011 ◽  
Vol 3 (6) ◽  
pp. 615-620
Author(s):  
Thomas J. Farmer ◽  
Ali Darwish ◽  
Benjamin Huebschman ◽  
Edward Viveiros ◽  
Mona E. Zaghloul
Keyword(s):  
Power Density ◽  
Millimeter Wave ◽  
High Power ◽  
Silicon Germanium ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Center Frequency ◽  
Two Stage ◽  
Chip Area ◽  
Power Added Efficiency

This paper presents measured results for two-stage and three-stage high-voltage/high-power (HiVP) amplifiers implemented in a commercial 0.12 μm silicon germanium (SiGe) heterojunction bipolar transistor (HBT) bipolar Complementary Metal Oxide Semiconductor (BiCMOS) process at millimeter wave. The HiVP configuration provides a new tool for millimeter-wave silicon designers to achieve large output voltage swings, high output power density, customizable bias, and a way to minimize, if not eliminate, matching circuitry at millimeter-wave frequencies. The two-stage amplifier has achieved a PSAT = 5.41 dBm with a power added efficiency (PAE) of 8.06% at center frequency 30 GHz. The three-stage amplifier has achieved a PSAT = 8.85 dBm with a PAE of 11.35% with a total chip area of 0.068 mm2 at center frequency 30 GHz. Simulation, layout, fabrication, and measurement results are presented in this paper.

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