Bipolar Analog Memristors as Artificial Synapses for Neuromorphic Computing

Synaptic devices with bipolar analog resistive switching behavior are the building blocks for memristor-based neuromorphic computing. In this work, a fully complementary metal-oxide semiconductor (CMOS)-compatible, forming-free, and non-filamentary memristive device (Pd/Al2O3/TaOx/Ta) with bipolar analog switching behavior is reported as an artificial synapse for neuromorphic computing. Synaptic functions, including long-term potentiation/depression, paired-pulse facilitation (PPF), and spike-timing-dependent plasticity (STDP), are implemented based on this device; the switching energy is around 50 pJ per spike. Furthermore, for applications in artificial neural networks (ANN), determined target conductance states with little deviation (<1%) can be obtained with random initial states. However, the device shows non-linear conductance change characteristics, and a nearly linear conductance change behavior is obtained by optimizing the training scheme. Based on these results, the device is a promising emulator for biology synapses, which could be of great benefit to memristor-based neuromorphic computing.

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A synaptic device built in one diode–one resistor (1D–1R) architecture with intrinsic SiOx-based resistive switching memory

Physical Sciences Reviews ◽

10.1515/psr-2016-0012 ◽

2016 ◽

Vol 1 (4) ◽

Author(s):

Yao-Feng Chang ◽

Burt Fowler ◽

Ying-Chen Chen ◽

Fei Zhou ◽

Chih-Hung Pan ◽

...

Keyword(s):

Resistive Switching ◽

Silicon Oxide ◽

Complementary Metal Oxide Semiconductor ◽

Long Term Potentiation ◽

Spike Timing ◽

Oxide Semiconductor ◽

Resistive Switching Memory ◽

Term Potentiation ◽

Switching Memory

Abstract We realize a device with biological synaptic behaviors by integrating silicon oxide (SiOx) resistive switching memory with Si diodes to further minimize total synaptic power consumption due to sneak-path currents and demonstrate the capability for spike-induced synaptic behaviors, representing critical milestones for the use of SiO2-based materials in future neuromorphic computing applications. Biological synaptic behaviors such as long-term potentiation, long-term depression, and spike-timing dependent plasticity are demonstrated systemically with comprehensive investigation of spike waveform analyses and represent a potential application for SiOx-based resistive switching materials. The resistive switching SET transition is modeled as hydrogen (proton) release from the (SiH)2 defect to generate the hydrogenbridge defect, and the RESET transition is modeled as an electrochemical reaction (proton capture) that re-forms (SiH)2. The experimental results suggest a simple, robust approach to realize programmable neuromorphic chips compatible with largescale complementary metal-oxide semiconductor manufacturing technology.

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A New Approach to the Fabrication of Memristive Neuromorphic Devices: Compositionally Graded Films

Materials ◽

10.3390/ma13173680 ◽

2020 ◽

Vol 13 (17) ◽

pp. 3680

Author(s):

Jong-Gul Yoon

Keyword(s):

Short Term Memory ◽

Chemical Vapor ◽

Complementary Metal Oxide Semiconductor ◽

Information Storage ◽

Oxide Semiconductor ◽

Film Electrode ◽

Retention Performance ◽

Short Term ◽

Neuromorphic Computing ◽

Term Memory

Energy-efficient computing paradigms beyond conventional von-Neumann architecture, such as neuromorphic computing, require novel devices that enable information storage at nanoscale in an analogue way and in-memory computing. Memristive devices with long-/short-term synaptic plasticity are expected to provide a more capable neuromorphic system compared to traditional Si-based complementary metal-oxide-semiconductor circuits. Here, compositionally graded oxide films of Al-doped MgxZn1−xO (g-Al:MgZnO) are studied to fabricate a memristive device, in which the composition of the film changes continuously through the film thickness. Compositional grading in the films should give rise to asymmetry of Schottky barrier heights at the film-electrode interfaces. The g-Al:MgZnO films are grown by using aerosol-assisted chemical vapor deposition. The current-voltage (I-V) and capacitance-voltage (C-V) characteristics of the films show self-rectifying memristive behaviors which are dependent on maximum applied voltage and repeated application of electrical pulses. Endurance and retention performance tests of the device show stable bipolar resistance switching (BRS) with a short-term memory effect. The short-term memory effects are ascribed to the thermally activated release of the trapped electrons near/at the g-Al:MgZnO film-electrode interface of the device. The volatile resistive switching can be used as a potential selector device in a crossbar memory array and a short-term synapse in neuromorphic computing.

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Low Temperature Sensitivity CMOS Transconductor Based on GZTC MOSFET Condition

Journal of Integrated Circuits and Systems ◽

10.29292/jics.v11i1.427 ◽

2016 ◽

Vol 11 (1) ◽

pp. 27-37

Author(s):

Pedro Toledo ◽

Hamilton Klimach ◽

David Cordova ◽

Sergio Bampi ◽

Eric Fabris

Keyword(s):

Analog Circuits ◽

Thermal Sensitivity ◽

Temperature Stability ◽

Complementary Metal Oxide Semiconductor ◽

Building Blocks ◽

Oxide Semiconductor ◽

Zero Temperature ◽

Strong Inversion ◽

Commercial Process ◽

Bias Condition

Complementary Metal Oxide Semiconductor (CMOS) Transconductors, or Gm cells, are key building blocks to implement a large variety of analog circuits such as adjustable filters, multipliers, controlled oscillators and amplifiers. Usually temperature stability is a must in such applications, and herein we define all required conditions to design low thermal sensitivity Gm cells by biasing MOSFETs at Transconductance Zero Temperature Condition (GZTC). This special bias condition is analyzed using a MOSFET model which is continuous from weak to strong inversion, and it is proved that this condition always occurs from moderate to strong inversion operation in any CMOS fabrication process. Additionally, a few example circuits are designed using this technique: a single-ended resistor emulator, an impedance inverter, a first order and a second order filter. These circuits have been simulated in a 130 nm CMOS commercial process, resulting in improved thermal stability in the main performance parameters, in the range from 27 to 53 ppm/oC.

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An Advanced 1-bit Arithmetic Logic Unit (ALU) with Hybrid Memristor-CMOS Architecture

10.36227/techrxiv.16587461.v1 ◽

2021 ◽

Author(s):

Muhammad Farhan Azmine ◽

Urmi Debnath ◽

Yeasir Arafat

Keyword(s):

Complementary Metal Oxide Semiconductor ◽

Logic Gates ◽

Building Blocks ◽

Oxide Semiconductor ◽

Memory Element ◽

Area Efficiency ◽

Arithmetic Logic Unit ◽

Non Volatile Memory ◽

Electrical Component ◽

Logic Unit

<div>Memristor is dubbed as the fourth fundamental electrical component which works primarily as a non-volatile memory element. Memristors can also be used to construct logic gates, and Memristor Ratioed Logic (MRL) is one of these structures. The higher area efficiency and CMOS architecture compatibility of MRL gates have lead researchers to pay attention to its use in digital logic architecture. In this work, binary MRL is integrated with Complementary Metal-Oxide Semiconductor(CMOS) logic elements to develop building blocks of an Arithmetic Logic Unit (ALU). The proposed 1-bit ALU is simulated using LTSpice, which allows the versatility of changing the parameters as per the model used. This work designs and analyses an optimized cascadable 1-bit ALU with with voltage level based binary logic state via simulation. The proposed circuit shows improvement in transistor count and delay over benchmark circuits.</div>

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Complementary Metal‐Oxide Semiconductor and Memristive Hardware for Neuromorphic Computing

Advanced Intelligent Systems ◽

10.1002/aisy.201900189 ◽

2020 ◽

Vol 2 (5) ◽

pp. 1900189 ◽

Cited By ~ 10

Author(s):

Mostafa Rahimi Azghadi ◽

Ying-Chen Chen ◽

Jason K. Eshraghian ◽

Jia Chen ◽

Chih-Yang Lin ◽

...

Keyword(s):

Metal Oxide ◽

Complementary Metal Oxide Semiconductor ◽

Metal Oxide Semiconductor ◽

Oxide Semiconductor ◽

Neuromorphic Computing

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CMOS-compatible photonic devices for single-photon generation

Nanophotonics ◽

10.1515/nanoph-2016-0022 ◽

2016 ◽

Vol 5 (3) ◽

pp. 427-439 ◽

Cited By ~ 14

Author(s):

Chunle Xiong ◽

Bryn Bell ◽

Benjamin J. Eggleton

Keyword(s):

Secure Communication ◽

Single Photon ◽

Complementary Metal Oxide Semiconductor ◽

Building Blocks ◽

Photonic Devices ◽

Oxide Semiconductor ◽

Single Photons ◽

Quantum Secure Communication ◽

Cmos Compatible ◽

Photon Generation

AbstractSources of single photons are one of the key building blocks for quantum photonic technologies such as quantum secure communication and powerful quantum computing. To bring the proof-of-principle demonstration of these technologies from the laboratory to the real world, complementary metal–oxide–semiconductor (CMOS)-compatible photonic chips are highly desirable for photon generation, manipulation, processing and even detection because of their compactness, scalability, robustness, and the potential for integration with electronics. In this paper, we review the development of photonic devices made from materials (e.g., silicon) and processes that are compatible with CMOS fabrication facilities for the generation of single photons.

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The Mixed Logic Style based Low Power and High Speed 3-2 Compressor for ASIC designs at 32nm Technology

International Journal of Engineering and Advanced Technology - Regular Issue ◽

10.35940/ijeat.a1027.109119 ◽

2019 ◽

Vol 9 (1) ◽

pp. 43-49

Keyword(s):

Power Consumption ◽

Low Power ◽

High Speed ◽

Average Power ◽

Complementary Metal Oxide Semiconductor ◽

Building Blocks ◽

Propagation Delay ◽

Oxide Semiconductor ◽

Logic Design ◽

Average Power Consumption

Compressors are the fundamental building blocks to construct Data Processing arithmetic units. A novel 3-2 Compressor is presented in this paper which is designed by Mixed logic design style. In addition to small size transistors and reduced transistor activity compared to conventional CMOS (Complementary Metal Oxide Semiconductor) gates, it provides the priority between the High logic and Low logic for the computation of the output. Various logic topologies are used to design the 3-2 compressor like High-Skew(Hi-Skew), Low-Skew(Li-Skew), TGL (Transmission Gate Logic) and DVL (Dual value Logic). This new approach gives the better operating speed, low power consumption compared to conventional logic design by reducing the transistors activity, improving the driving capability and reduced input capacitance with skew gates. Especially the Mixed logic style-3 provides 92.39% average power consumption and Propagation Delay of 99.59% at 0.8v. The H-SPICE simulation tool is used for construction and evaluation of compressor logic at different voltages. 32nm model file is used for MOS transistors

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Flexible and Energy-efficient Synaptic Transistor with Quasi-linear Weight Update Protocol by Inkjet Printing of Orientated Polar-electret/High-k Oxide Hybrid Dielectric

10.21203/rs.3.rs-677781/v1 ◽

2021 ◽

Author(s):

Yushan Li ◽

Wei Cai ◽

Ruiqiang Tao ◽

Wentao Shuai ◽

Jingjing Rao ◽

...

Keyword(s):

Inkjet Printing ◽

Low Voltage ◽

Learning Experience ◽

Low Cost ◽

Learning Rule ◽

Long Term Potentiation ◽

Spike Timing ◽

Dipole Orientation ◽

Synaptic Dynamics ◽

Conductance States

Abstract Artificial synapse by inkjet printing is promising in cost-effective and flexible applications, but remains challenging in emulating synaptic dynamics with a sufficient number of stable and effective conductance states under ultra-low voltage spiking operation. Hence, for the first time, a synaptic transistor gated by inkjet-printed hybrid dielectric of electret polyvinyl pyrrolidone (PVP) and high-k Zirconia oxide (ZrOx) is proposed and thus synthesized to solve this issue. Quasi-linear potentiation/depression characteristics with large variation margin of conductance states are obtained through the coupling of these two dielectric components and the facilitating of dipole orientation, which can be attributed to the orderly arranged molecule chains induced by the carefully designed microfluidic flows in droplets. Crucial features of biological synapses including long-term potentiation/depression (LTP/D), spike-timing-dependence-plasticity (STDP) learning rule, “Learning-Experience” behavior, and ultralow energy consumption (< 10 fJ/pulse) are successfully implemented on the device. Simulation results exhibit an excellent image recognition accuracy (97.1 %) after 15 training epochs, which is the highest for printed synaptic transistors. Moreover, the device sustained excellent endurance against bending tests with radius down to 8 mm. This work presents a very viable solution for constructing the futuristic flexible and low-cost neural systems.

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STDP implementation using multi-state spin-orbit torque synapse

Semiconductor Science and Technology ◽

10.1088/1361-6641/ac419c ◽

2021 ◽

Author(s):

Hamdam Ghanatian ◽

Margherita Ronchini ◽

Hooman Farkhani ◽

Farshad Moradi

Keyword(s):

Learning Algorithm ◽

Magnetic Tunnel Junction ◽

Complementary Metal Oxide Semiconductor ◽

Cmos Technology ◽

Spike Timing ◽

Oxide Semiconductor ◽

Spin Orbit ◽

Ultra Low Power ◽

Artificial Neural Network Ann ◽

State Spin

Abstract The abundance of data to be processed calls for new computing paradigms, which could accommodate, and directly map artificial neural network (ANN) architectures at the hardware level. Neuromorphic computing has emerged as a potential solution, proposing the implementation of artificial neurons and synapses on physical substrates. Conventionally, neuromorphic platforms are deployed in complementary metal-oxide–semiconductor (CMOS) technology. However, such implementations still cannot compete with the highly energy-efficient performance of the brain. This calls for novel ultra-low-power nano-scale devices with the possibility of upscaling for the implementation of complex networks. In this paper, a multi-state spin-orbit torque (SOT) synapse based on the three-terminal perpendicular-anisotropy magnetic tunnel junction (P-MTJ) is proposed. In this implementation, P-MTJs use common heavy metals (HMs) but with different cross-section areas, thereby creating multiple states that can be harnessed to implement synapses. The proposed multi-state SOT synapse can solve the state-limited issue of spin-based synapses. Moreover, it is shown that the proposed multi-state SOT synapse can be programmed to reproduce the spike-timing-dependent plasticity (STDP) learning algorithm.

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