A 10-BIT 0.5 V 100 kS/s SAR ADC WITH A NEW RAIL-TO-RAIL COMPARATOR FOR ENERGY LIMITED APPLICATIONS

2014 ◽  
Vol 23 (02) ◽  
pp. 1450026 ◽  
Author(s):  
REZA INANLOU ◽  
MOHAMMAD YAVARI
Keyword(s):  
Power Consumption ◽  
Signal To Noise Ratio ◽  
Average Power ◽  
Cmos Process ◽  
Signal To Noise ◽  
Digital To Analog Converter ◽  
Analog To Digital ◽  
Offset Voltage ◽  
Rail To Rail ◽  
Average Power Consumption

In this paper, a 10-bit 0.5 V 100 kS/s successive approximation register (SAR) analog-to-digital converter (ADC) with a new fully dynamic rail-to-rail comparator is presented. The proposed comparator enhances the input signal range to the rail-to-rail mode, and hence, improves the signal-to-noise ratio (SNR) of the ADC in low supply voltages. The effect of the latch offset voltage is reduced by providing a higher voltage gain in the regenerative latch. To reduce the ADC power consumption further, the binary-weighted capacitive array with an attenuation capacitor (BWA) is employed as the digital-to-analog converter (DAC) in this design. The ADC is designed and simulated in a 90 nm CMOS process with a single 0.5 V power supply. Spectre simulation results show that the average power consumption of the proposed ADC is about 400 nW and the peak signal-to-noise plus distortion ratio (SNDR) is 56 dB. By considering 10% increase in total ADC power consumption due to the parasitics and a loss of 0.22 LSB in ENOB due to the DAC capacitors mismatch, the achieved figure of merit (FoM) is 11.4 fJ/conversion-step.

scholarly journals A Novel Cross-Latch Shift Register Scheme for Low Power Applications

2020 ◽  
Vol 11 (1) ◽  
pp. 129
Author(s):  
Po-Yu Kuo ◽  
Ming-Hwa Sheu ◽  
Chang-Ming Tsai ◽  
Ming-Yan Tsai ◽  
Jin-Fa Lin
Keyword(s):  
Power Consumption ◽  
Supply Voltage ◽  
Electrical Power ◽  
Average Power ◽  
Leakage Power ◽  
Shift Register ◽  
Cmos Process ◽  
Average Power Consumption ◽  
Simulation Results ◽  
Layout Area

The conventional shift register consists of master and slave (MS) latches with each latch receiving the data from the previous stage. Therefore, the same data are stored in two latches separately. It leads to consuming more electrical power and occupying more layout area, which is not satisfactory to most circuit designers. To solve this issue, a novel cross-latch shift register (CLSR) scheme is proposed. It significantly reduced the number of transistors needed for a 256-bit shifter register by 48.33% as compared with the conventional MS latch design. To further verify its functions, this CLSR was implemented by using TSMC 40 nm CMOS process standard technology. The simulation results reveal that the proposed CLSR reduced the average power consumption by 36%, cut the leakage power by 60.53%, and eliminated layout area by 34.76% at a supply voltage of 0.9 V with an operating frequency of 250 MHz, as compared with the MS latch.

scholarly journals A Low-Power 12-Bit 20 MS/s Asynchronously Controlled SAR ADC for WAVE ITS Sensor Based Applications

Sensors ◽  
2021 ◽  
Vol 21 (7) ◽  
pp. 2260
Author(s):  
Khuram Shehzad ◽  
Deeksha Verma ◽  
Danial Khan ◽  
Qurat Ul Ain ◽  
Muhammad Basim ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Intelligent Transportation System ◽  
Cmos Process ◽  
Process Technology ◽  
Back Issue ◽  
Digital To Analog Converter ◽  
Analog To Digital ◽  
Switching Method

A low power 12-bit, 20 MS/s asynchronously controlled successive approximation register (SAR) analog-to-digital converter (ADC) to be used in wireless access for vehicular environment (WAVE) intelligent transportation system (ITS) sensor based application is presented in this paper. To optimize the architecture with respect to power consumption and performance, several techniques are proposed. A switching method which employs the common mode charge recovery (CMCR) switching process is presented for capacitive digital-to-analog converter (CDAC) part to lower the switching energy. The switching technique proposed in our work consumes 56.3% less energy in comparison with conventional CMCR switching method. For high speed operation with low power consumption and to overcome the kick back issue in the comparator part, a mutated dynamic-latch comparator with cascode is implemented. In addition, to optimize the flexibility relating to the performance of logic part, an asynchronous topology is employed. The structure is fabricated in 65 nm CMOS process technology with an active area of 0.14 mm2. With a sampling frequency of 20 MS/s, the proposed architecture attains signal-to-noise distortion ratio (SNDR) of 65.44 dB at Nyquist frequency while consuming only 472.2 µW with 1 V power supply.

scholarly journals A CMOS-Thyristor Based Temperature Sensor with +0.37 °C/−0.32 °C Inaccuracy

Micromachines ◽  
2020 ◽  
Vol 11 (2) ◽  
pp. 124 ◽  
Author(s):  
Jing Li ◽  
Yuyu Lin ◽  
Siyuan Ye ◽  
Kejun Wu ◽  
Ning Ning ◽  
...  
Keyword(s):  
Power Consumption ◽  
Temperature Sensor ◽  
Current Source ◽  
Average Power ◽  
Bias Current ◽  
Cmos Process ◽  
Linear Temperature ◽  
Temperature Characteristics ◽  
Period Ratio ◽  
Average Power Consumption

This paper describes a voltage controlled oscillator (VCO) based temperature sensor. The VCOs are composed of complementary metal–oxide–semiconductor (CMOS) thyristor with the advantage of low power consumption. The period of the VCO is temperature dependent and is function of the transistors’ threshold voltage and bias current. To obtain linear temperature characteristics, this paper constructed the period ratio between two different-type VCOs. The period ratio is independent of the temperature characteristics from current source, which makes the bias current generator simplified. The temperature sensor was designed in 130 nm CMOS process and it occupies an active area of 0.06 mm2. Based on the post-layout simulation results, after a first-order fit, the sensor achieves an inaccuracy of +0.37/−0.32 °C from 0 °C to 80 °C, while the average power consumption of the sensor at room temperature is 156 nW.

VCO-BASED CONTINUOUS-TIME SIGMA DELTA ADC BASED ON A DUAL-VCO-QUANTIZER-LOOP STRUCTURE

2013 ◽  
Vol 22 (09) ◽  
pp. 1340013 ◽  
Author(s):  
Z. T. XU ◽  
X. L. ZHANG ◽  
J. Z. CHEN ◽  
S. G. HU ◽  
Q. YU ◽  
...  
Keyword(s):  
Continuous Time ◽  
Signal To Noise Ratio ◽  
Quantization Noise ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Loop Structure ◽  
Signal To Noise ◽  
Sigma Delta ◽  
Analog To Digital ◽  
Sigma Delta Adc

This paper explores a continuous time (CT) sigma delta (ΣΔ) analog-to-digital converter (ADC) based on a dual-voltage-controlled oscillator (VCO)-quantizer-loop structure. A third-order filter is adopted to reduce quantization noise and VCO nonlinearity. Even-order harmonics of VCO are significantly reduced by the proposed dual-VCO-quantizer-loop structure. The prototype with 10 MHz bandwidth and 400 MHz clock rate is designed using a 0.18 μm RF CMOS process. Simulation results show that the signal-to-noise ratio and signal-to-noise distortion ratio (SNDR) are 76.9 and 76 dB, respectively, consuming 37 mA at 1.8 V. The key module of the ADC, which is a 4-bit VCO-based quantizer, can convert the voltage signal into a frequency signal and quantize the corresponding frequency to thermometer codes at 400 MS/s.

A 3.03 μW 10-BIT 200 KS/s SAR ADC IN 0.18 μM CMOS

2013 ◽  
Vol 22 (04) ◽  
pp. 1350026 ◽  
Author(s):  
ZHANGMING ZHU ◽  
YU XIAO ◽  
LIANG LIANG ◽  
LIANXI LIU ◽  
YINTANG YANG
Keyword(s):  
Power Consumption ◽  
Figure Of Merit ◽  
Cmos Process ◽  
Control Logic ◽  
Signal To Noise ◽  
Dynamic Comparator ◽  
Switching Sequence ◽  
Analog To Digital ◽  
Static Power ◽  
Simulation Results

Based on TSMC 0.18 μm 1.8 V CMOS process, a low power 10-bit 200 KS/s successive approximation register (SAR) analog-to-digital (ADC) is realized. This paper mainly considers the improvement of linearity and the optimization of power consumption. And a novel switching sequence is proposed which allows both to achieve a better compromise. Moreover, the fully dynamic comparator, which consumes no static power, and the optimization of SAR control logic, further reduce power consumption. The simulation results show that at 1.0 V supply and 200 KS/s, the ADC achieves an signal-to-noise and distortion-ration (SNDR) of 59.78 dB and consumes 3.03 μW, resulting in a figure-of-merit (FOM) of 19.0 fJ/conversion-step. The ADC core occupies an active area of only 260 × 220 μm2.

scholarly journals A 14-bit High Speed 125MS/s Low Power SAR ADC using Dual Split Capacitor DAC Architecture in 90nm CMOS Technology

2021 ◽  
Vol 15 ◽  
pp. 556-568
Author(s):  
Chaya Shetty ◽  
M. Nagabushanam ◽  
Venkatesh Nuthan Prasad
Keyword(s):  
High Speed ◽  
Signal To Noise Ratio ◽  
Sampling Rate ◽  
Cmos Technology ◽  
Sar Adc ◽  
Cmos Process ◽  
Digital To Analog Converter ◽  
Additional Advantage ◽  
Analog To Digital ◽  
Split Capacitor

The proposed work presents a High speed 14-bit 125MS/s successive-approximation-register asynchronous analog-to-digital-converter (SAR-ADC). A novel-based Dual-Split-Array-Three-Section (DSATS) capacitor DAC (DSATS-CDAC) is employed to increase the linearity and energy efficiency of the digital-to-analog converter (DAC), additional advantage of this work is that, the area is reduced by 59.76% of conventional design. The proposed switching technique of the (DSATS-CDAC) consumes less switching energy. Additionally, bootstrap switching is employed to ensure improved linearity and reduced power consumption.in order to enhance the speed of operation and increase the precision a preamplifier latch based comparator is implemented with the delay of 250ps. The proposed SAR-ADC prototype is implemented in a 90nm CMOS process and consumes a power of 42.8mW at 1V operating supply. The proposed design achieves a figure of merit (FOM) of 37.43 fJ/conversion-step, signal-to-noise-ratio (SNR) of 81 dB, and an effective-number-of-bits (ENOB) of 13.16 bits with a sampling rate of 125MS/s.

Study on Fast Algorithm for SNR and Method for Threshold Confirmation

2013 ◽  
Vol 427-429 ◽  
pp. 1718-1722
Author(s):  
Lin Sun ◽  
Ran Wei ◽  
Fu Ting Bao ◽  
Xian Zhang Tian
Keyword(s):  
Power Spectrum ◽  
Fast Algorithm ◽  
Human Gene ◽  
Signal To Noise Ratio ◽  
Average Power ◽  
Threshold Value ◽  
Computational Experiments ◽  
Rigorous Derivation ◽  
Signal To Noise ◽  
Average Power Spectrum

To reduce the amount of computing resources, a fast algorithm of the average power spectrum and signal-to-noise ratio was presented based on rigorous derivation of the formula. Also, it proved the rule gained from computational experiments. Besides, a method called fitting-optimization to determine the classification threshold value was proposed. It improves the accuracy by about 7% for human gene.

Designing of Low-Power High-Speed Noise Immune CNTFET 1-Trit Unbalanced Ternary Subtractor

2021 ◽  
Author(s):  
Yogesh Shrivastava ◽  
Tarun Kumar Gupta
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
Noise Analysis ◽  
Average Power ◽  
Noise Margin ◽  
Average Power Consumption ◽  
Effect Transistor ◽  
Power Delay Product ◽  
Static Noise ◽  
Made In

Ternary logic has been demonstrated as a superior contrasting option to binary logic. This paper presents a ternary subtractor circuit in which the input signal is converted into binary. The proposed design is implemented using Carbon Nanotube Field Effect Transistor (CNTFET), a forefront innovation. A correlation has been made in the proposed design on parameters like Power-Delay Product (PDP), Energy Delay Product (EDP), average power consumption, delay and static noise margin. Every one of these parameters is obtained by simulating the circuits on the HSPICE simulator. The proposed design indicates an improvement of 60.14%, 59.34%, 74.98% and 84.28%, respectively, in power consumption, delay, PDP and EDP individually in correlation with recent designs. The increased carbon nanotubes least affect the proposed subtractor design. In noise analysis, the proposed design outperformed all the existing designs.

scholarly journals The Characteristics of Metaheuristic Method in Selection of Path Pairs on Multicriteria Ad Hoc Networks

2019 ◽  
Vol 2019 ◽  
pp. 1-6 ◽  
Author(s):  
Nyoman Gunantara ◽  
I Dewa Nyoman Nurweda Putra
Keyword(s):  
Power Consumption ◽  
Ad Hoc Network ◽  
Ad Hoc ◽  
Signal To Noise Ratio ◽  
Computing Time ◽  
Signal To Noise ◽  
Swarm Optimization ◽  
Metaheuristic Methods ◽  
Hoc Networks ◽  
Selection Of

This research analyzes the metaheuristic methods, that is, ant colony optimization (ACO), genetic algorithm (GA), and particle swarm optimization (PSO), in the selection of path pairs on multicriteria ad hoc network. Multicriteria used are signal-to-noise ratio (SNR), load variance, and power consumption. Analysis of the simulation result is done as follows: first, in terms of computing time, the ACO method takes the most time compared with GA and PSO methods. Second, in terms of multicriteria performance, i.e., the performance of SNR, load variance, and power consumption, the GA method shows the same value in each repetition. It is different from ACO and PSO that show varying values. Finally, the selection of the path pairs by the GA method indicates the pairs of the path that are always the same as by the ACO and PSO methods indicate those that vary.

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