scholarly journals A Current-Mode TransImpedance Amplifier for Capacitive Sensors

Proceedings ◽  
2018 ◽  
Vol 2 (13) ◽  
pp. 1033
Author(s):  
Alessandro Nastro ◽  
Andrea De Marcellis ◽  
Marco Ferrari ◽  
Vittorio Ferrari

A Current-Mode (CM) TransImpedance Amplifier (TIA) based on Second Generation Current Conveyors (CCIIs) for capacitive microsensor measurements is presented. The designed electronic interface performs a capacitance-to-voltage conversion using 3 CCIIs and 3 resistors exploiting a synchronous-demodulation technique to improve the overall detection sensitivity and resolution of the system. A CM-TIA solution designed at transistor level in AMS0.35 µm integrated CMOS technology with a power consumption lower than 900 µW is proposed. Experimental results obtained with a board-level prototype show linear behavior of the proposed interface circuit with a resolution up to 34.5 fF and a sensitivity up to 223 mV/nF, confirming the theoretical expectations.

2013 ◽  
Vol 22 (09) ◽  
pp. 1340001 ◽  
Author(s):  
JIUN-WEI HORNG ◽  
TO-YAO CHIU ◽  
CHING-PAO HSIAO ◽  
GUANG-TING HUANG

A current-mode universal biquadratic filter with three input terminals and one output terminal is presented. The architecture uses two current conveyors (CCs), two grounded capacitors and two grounded resistors; and can realize all standard second-order filter functions — highpass, bandpass, lowpass, notch and allpass. Moreover, the circuit still offers the following advantage features: very low active and passive sensitivities, using of grounded capacitors and resistors which is ideal for integrated circuit implementation, without requirements for critical component matching conditions and very high output impedance. The workability of the proposed circuit has been verified via HSPICE simulations using TSMC 0.18 μm, level 49 MOSFET technology.


Author(s):  
B.T. Krishna ◽  
◽  
Shaik. mohaseena Salma ◽  

A flux-controlled memristor using complementary metal–oxide–(CMOS) structure is presented in this study. The proposed circuit provides higher power efficiency, less static power dissipation, lesser area, and can also reduce the power supply by using CMOS 90nm technology. The circuit is implemented based on the use of a second-generation current conveyor circuit (CCII) and operational transconductance amplifier (OTA) with few passive elements. The proposed circuit uses a current-mode approach which improves the high frequency performance. The reduction of a power supply is a crucial aspect to decrease the power consumption in VLSI. An offered emulator in this proposed circuit is made to operate incremental and decremental configurations well up to 26.3 MHZ in cadence virtuoso platform gpdk using 90nm CMOS technology. proposed memristor circuit has very little static power dissipation when operating with ±1V supply. Transient analysis, memductance analysis, and dc analysis simulations are verified practically with the Experimental demonstration by using ideal memristor made up of ICs AD844AN and CA3080, using multisim which exhibits theoretical simulation are verified and discussed.


2015 ◽  
Vol 63 (4) ◽  
pp. 919-922 ◽  
Author(s):  
P. Śniatała ◽  
M. Naumowicz ◽  
A. Handkiewicz ◽  
S. Szczęsny ◽  
J.L.A. de Melo ◽  
...  

Abstract The paper presents a second order current mode sigma-delta modulator designed with the help of a new elaborated tool to optimize the transistor sizes. The circuit is composed of two continuous time loop filters, a current comparator and a one bit DAC with a current output. The resulting circuit, designed in a 65 nm 1.2 V CMOS technology, has a bandwidth of 2 MHz for a clock frequency of 250 MHz. The electrical simulation results show that it achieves a maximum signal-to-noise-plus-distortion ratio (SNDR) of 53.6 dB while dissipating 93 μW, which corresponds to an efficiency of 59.7 fJ/conv. The fully current mode structure makes the circuit suitable to be applied in a current mode signal processing like biosensors or image pixels arrays.


2019 ◽  
Vol 70 (4) ◽  
pp. 323-328
Author(s):  
Dan-Dan Zheng ◽  
Yu-Bin Li ◽  
Chang-Qi Wang ◽  
Kai Huang ◽  
Xiao-Peng Yu

Abstract In this paper, an area and power efficient current mode frequency synthesizer for system-on-chip (SoC) is proposed. A current-mode transformer loop filter suitable for low supply voltage is implemented to remove the need of a large capacitor in the loop filter, and a current controlled oscillator with additional voltage based frequency tuning mechanism is designed with an active inductor. The proposed design is further integrated with a fully programmable frequency divider to maintain a good balance among output frequency operating range, power consumption as well as silicon area. A test chip is implemented in a standard 0.13 µm CMOS technology, measurement result demonstrates that the proposed design has a working range from 916 MHz to 1.1 l GHz and occupies a silicon area of 0.25 mm2 while consuming 8.4 mW from a 1.2 V supply.


2013 ◽  
Vol 2013 ◽  
pp. 1-8 ◽  
Author(s):  
Worapong Tangsrirat

This paper describes the conception of the current follower transconductance amplifier (CFTA) with electronically and linearly current tunable. The newly modified element is realized based on the use of transconductance cells (Gms) as core circuits. The advantage of this element is that the current transfer ratios (iz/ipandix/iz) can be tuned electronically and linearly by adjusting external DC bias currents. The circuit is designed and analyzed in 0.35 μm TSMC CMOS technology. Simulation results for the circuit with ±1.25 V supply voltages show that it consumes only 0.43 mw quiescent power with 70 MHz bandwidth. As an application example, a current-mode KHN biquad filter is designed and simulated.


2017 ◽  
Vol 24 (1) ◽  
pp. 79-89
Author(s):  
Bogdan Pankiewicz

Abstract In this paper a programmable input mode instrumentation amplifier (IA) utilising second generation, multiple output current conveyors and transmission gates is presented. Its main advantage is the ability to choose a voltage or current mode of inputs by setting the voltage of two configuration nodes. The presented IA is prepared as an integrated circuit block to be used alone or as a sub-block in a microcontroller or in a field programmable gate array (FPGA), which shall condition analogue signals to be next converted by an analogue-to-digital converter (ADC). IA is designed in AMS 0.35 µm CMOS technology and the power supply is 3.3 V; the power consumption is approximately 9.1 mW. A linear input range in the voltage mode reaches ± 1.68 V or ± 250 µA in current mode. A passband of the IA is above 11 MHz. The amplifier works in class A, so its current supply is almost constant and does not cause noise disturbing nearby working precision analogue circuits.


2011 ◽  
Vol 2011 ◽  
pp. 1-7 ◽  
Author(s):  
Neeta Pandey ◽  
Sajal K. Paul

A universal voltage-mode filter (VM) and a current-mode filter (CM) based on recently proposed active building block, namely, differential voltage current conveyor transconductance amplifier (DVCCTA) are proposed. Both the circuits use a single DVCCTA, two capacitors, and a single resistor. The filters enjoy low-sensitivity performance and low component spread and exhibit electronic tunability of filter parameters via bias currents of DVCCTA. SPICE simulation using 0.25 μm TSMC CMOS technology parameters is included to show the workability of the proposed circuits.


2011 ◽  
Vol 2011 ◽  
pp. 1-10 ◽  
Author(s):  
Neeta Pandey ◽  
Sajal K. Paul

A new active building block for analog signal processing, namely, differential difference current conveyor transconductance amplifier (DDCCTA), is presented, and performance is checked through PSPICE simulations which show the usability of the proposed element is up to 201 MHz. The proposed block is implemented using 0.25 μm TSMC CMOS technology. Some of the applications are presented using the proposed DDCCTA, namely, a voltage mode multifunction filter, a current mode universal filter, an oscillator, current and voltage amplifiers, and grounded inductor simulator. The feasibility of DDCCTA and its applications is confirmed via PSPICE simulations.


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