scholarly journals Multipurpose Bio-Monitored Integrated Circuit in a Contact Lens Eye-Tracker

Sensors ◽  
2022 ◽  
Vol 22 (2) ◽  
pp. 595
Author(s):  
Loïc Massin ◽  
Cyril Lahuec ◽  
Fabrice Seguin ◽  
Vincent Nourrit ◽  
Jean-Louis de Bougrenet de la Tocnaye
Keyword(s):  
Contact Lens ◽  
Integrated Circuit ◽  
Supply Voltage ◽  
Operating Time ◽  
Complementary Metal Oxide Semiconductor ◽  
Process Variations ◽  
Oxide Semiconductor ◽  
Gaze Direction ◽  
Eye Tracker ◽  
The Gaze

We present the design, fabrication, and test of a multipurpose integrated circuit (Application Specific Integrated Circuit) in AMS 0.35 µm Complementary Metal Oxide Semiconductor technology. This circuit is embedded in a scleral contact lens, combined with photodiodes enabling the gaze direction detection when illuminated and wirelessly powered by an eyewear. The gaze direction is determined by means of a centroid computation from the measured photocurrents. The ASIC is used simultaneously to detect specific eye blinking sequences to validate target designations, for instance. Experimental measurements and validation are performed on a scleral contact lens prototype integrating four infrared photodiodes, mounted on a mock-up eyeball, and combined with an artificial eyelid. The eye-tracker has an accuracy of 0.2°, i.e., 2.5 times better than current mobile video-based eye-trackers, and is robust with respect to process variations, operating time, and supply voltage. Variations of the computed gaze direction transmitted to the eyewear, when the eyelid moves, are detected and can be interpreted as commands based on blink duration or using blinks alternation on both eyes.

scholarly journals Effects of Process Variations in a HCMOS IC using a Monte Carlo SPICE Simulation

2017 ◽  
pp. 11-16
Author(s):  
Widianto Widianto ◽  
Lailis Syafaah ◽  
Nurhadi Nurhadi
Keyword(s):  
Monte Carlo ◽  
Integrated Circuit ◽  
High Speed ◽  
Evaluation Method ◽  
Complementary Metal Oxide Semiconductor ◽  
Process Variations ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Spice Simulation ◽  
Simulation Results

In this paper, effects of process variations in a HCMOS (High-Speed Complementary Metal Oxide Semiconductor) IC (Integrated Circuit) are examined using a Monte Carlo SPICE (Simulation Program with Integrated Circuit Emphasis) simulation. The variations of the IC are L and VTO variations. An evaluation method is used to evaluate the effects of the variations by modeling it using a normal (Gaussian) distribution. The simulation results show that the IC may be detected as a defective IC caused by the variations based on large supply currents flow to it. 

A Scalable Fully-Digital Differential Analog Voltage Comparator

2021 ◽  
Author(s):  
Ashima Gupta ◽  
Anil Singh ◽  
Alpana Agarwal
Keyword(s):  
Supply Voltage ◽  
Complementary Metal Oxide Semiconductor ◽  
Process Variations ◽  
Digital Design ◽  
Oxide Semiconductor ◽  
Design Environment ◽  
Worst Case ◽  
Voltage Comparator ◽  
Offset Voltage ◽  
Analog Voltage

This paper presents a scalable Fully-digital differential analog voltage comparator designed in Semi-Conductor Laboratory (SCL) 180[Formula: see text]nm complementary metal-oxide semiconductor technology. The proposed design is based on a digital design approach and is easily configurable to lower technology nodes. This design methodology makes the circuit less sensitive to process variations and takes fewer design efforts suitable for Systems-on-a-Chips (SOCs) application. The proposed circuit is designed and simulated in Cadence Virtuoso Analog Design Environment at the supply voltage ranging from 1[Formula: see text]V to 1.8[Formula: see text]V. The fully-digital analog voltage comparator has been synthesized using Synopsys Design Vision and auto-placed & auto-routed using Synopsys IC Compiler. This proposed comparator has a resolution of up to 7-bit at a supply voltage of 1.8[Formula: see text]V and a worst-case operating frequency of about 750 MHz at the TT corner. The obtained value of the offset voltage and delay is 0.55[Formula: see text]mV and 0.72 ns, respectively. The simulated results have shown that the power dissipation of the proposed scalable analog voltage comparator is [Formula: see text][Formula: see text]V and [Formula: see text][Formula: see text]V supply voltage, respectively. Also, the RC extracted post-layout simulations have been implemented to verify the performance, which does not affect the results much.

scholarly journals Investigation of PVT-Aware STT-MRAM Sensing Circuits for Low-VDD Scenario

Micromachines ◽  
2021 ◽  
Vol 12 (5) ◽  
pp. 551
Author(s):  
Zhongjian Bian ◽  
Xiaofeng Hong ◽  
Yanan Guo ◽  
Lirida Naviner ◽  
Wei Ge ◽  
...  
Keyword(s):  
Nonvolatile Memory ◽  
High Speed ◽  
Low Voltage ◽  
Supply Voltage ◽  
Random Access ◽  
Magnetic Tunnel Junction ◽  
Complementary Metal Oxide Semiconductor ◽  
Current Mode ◽  
Cmos Technology ◽  
Oxide Semiconductor

Spintronic based embedded magnetic random access memory (eMRAM) is becoming a foundry validated solution for the next-generation nonvolatile memory applications. The hybrid complementary metal-oxide-semiconductor (CMOS)/magnetic tunnel junction (MTJ) integration has been selected as a proper candidate for energy harvesting, area-constraint and energy-efficiency Internet of Things (IoT) systems-on-chips. Multi-VDD (low supply voltage) techniques were adopted to minimize energy dissipation in MRAM, at the cost of reduced writing/sensing speed and margin. Meanwhile, yield can be severely affected due to variations in process parameters. In this work, we conduct a thorough analysis of MRAM sensing margin and yield. We propose a current-mode sensing amplifier (CSA) named 1D high-sensing 1D margin, high 1D speed and 1D stability (HMSS-SA) with reconfigured reference path and pre-charge transistor. Process-voltage-temperature (PVT) aware analysis is performed based on an MTJ compact model and an industrial 28 nm CMOS technology, explicitly considering low-voltage (0.7 V), low tunneling magnetoresistance (TMR) (50%) and high temperature (85 °C) scenario as the worst sensing case. A case study takes a brief look at sensing circuits, which is applied to in-memory bit-wise computing. Simulation results indicate that the proposed high-sensing margin, high speed and stability sensing-sensing amplifier (HMSS-SA) achieves remarkable performance up to 2.5 GHz sensing frequency. At 0.65 V supply voltage, it can achieve 1 GHz operation frequency with only 0.3% failure rate.

Review: Static and Dynamic Analysis Methods for Multi-Branch Biasing Circuits

2018 ◽  
Vol 27 (13) ◽  
pp. 1830008
Author(s):  
Jin Wu ◽  
Pengfei Dai ◽  
Jie Peng ◽  
Lixia Zheng ◽  
Weifeng Sun
Keyword(s):  
Feedback Loop ◽  
Supply Voltage ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Critical Parameters ◽  
Cmos Process ◽  
Stable Equilibrium Point ◽  
Static And Dynamic Analysis ◽  
Text Structures ◽  
Different Types

The fundamental theories and primary structures for the multi-branch self-biasing circuits are reviewed in this paper. First, the [Formula: see text]/[Formula: see text] and [Formula: see text]/[Formula: see text] structures illustrating the static current definition mechanism are presented, including the conditions of starting up and entering into a stable equilibrium point. Then, the AC method based on the loop gain evaluation is utilized to analyze different types of circuits. On this basis, the laws which can couple the branches of self-biasing circuits to construct a suitable close feedback loop are summarized. By adopting Taiwan Semiconductor Manufacturing Company (TSMC)’s 0.18[Formula: see text][Formula: see text]m complementary metal–oxide–semiconductor (CMOS) process with 1.8[Formula: see text][Formula: see text] supply voltage, nearly all the circuits mentioned in the paper are simulated in the same branch current condition, which is close to the corresponding calculated results. Therefore, the methods summarized in this paper can be utilized for distinguishing, constructing, and optimizing critical parameters for various structures of the self-biasing circuits.

scholarly journals Angular Light, Polarization and Stokes Parameters Information in a Hybrid Image Sensor with Division of Focal Plane

Sensors ◽  
2020 ◽  
Vol 20 (12) ◽  
pp. 3391
Author(s):  
Francelino Freitas Carvalho ◽  
Carlos Augusto de Moraes Cruz ◽  
Greicy Costa Marques ◽  
Kayque Martins Cruz Damasceno
Keyword(s):  
Integrated Circuit ◽  
Incident Angle ◽  
Complementary Metal Oxide Semiconductor ◽  
Image Sensor ◽  
Light Polarization ◽  
Oxide Semiconductor ◽  
Stokes Parameters ◽  
New Paradigm ◽  
Depth Sensing ◽  
3D Image Reconstruction

Targeting 3D image reconstruction and depth sensing, a desirable feature for complementary metal oxide semiconductor (CMOS) image sensors is the ability to detect local light incident angle and the light polarization. In the last years, advances in the CMOS technologies have enabled dedicated circuits to determine these parameters in an image sensor. However, due to the great number of pixels required in a cluster to enable such functionality, implementing such features in regular CMOS imagers is still not viable. The current state-of-the-art solutions require eight pixels in a cluster to detect local light intensity, incident angle and polarization. The technique to detect local incident angle is widely exploited in the literature, and the authors have shown in previous works that it is possible to perform the job with a cluster of only four pixels. In this work, the authors explore three novelties: a mean to determine three of four Stokes parameters, the new paradigm in polarization cluster-pixel design, and the extended ability to detect both the local light angle and intensity. The features of the proposed pixel cluster are demonstrated through simulation program with integrated circuit emphasis (SPICE) of the regular Quadrature Pixel Cluster and Polarization Pixel Cluster models, the results of which are compliant with experimental results presented in the literature.

scholarly journals A 45 nm CMOS Avalanche Photodiode with 8.4-GHz Bandwidth

Micromachines ◽  
2020 ◽  
Vol 11 (1) ◽  
pp. 65
Author(s):  
Wenhao Zhi ◽  
Qingxiao Quan ◽  
Pingping Yu ◽  
Yanfeng Jiang
Keyword(s):  
Optical Communication ◽  
Integrated Circuit ◽  
Communication Systems ◽  
Complementary Metal Oxide Semiconductor ◽  
Avalanche Photodiode ◽  
Cmos Technology ◽  
Optical Signal ◽  
Oxide Semiconductor ◽  
Monolithically Integrated ◽  
Process Modification

Photodiode is one of the key components in optoelectronic technology, which is used to convert optical signal into electrical ones in modern communication systems. In this paper, an avalanche photodiode (APD) is designed and fulfilled, which is compatible with Taiwan Semiconductor Manufacturing Company (TSMC) 45-nm standard complementary metal–oxide–semiconductor (CMOS) technology without any process modification. The APD based on 45 nm process is beneficial to realize a smaller and more complex monolithically integrated optoelectronic chip. The fabricated CMOS APD operates at 850 nm wavelength optical communication. Its bandwidth can be as high as 8.4 GHz with 0.56 A/W responsivity at reverse bias of 20.8 V. Its active area is designed to be 20 × 20 μm2. The Simulation Program with Integrated Circuit Emphasis (SPICE) model of the APD is also proposed and verified. The key parameters are extracted based on its electrical, optical and frequency responses by parameter fitting. The device has wide potential application for optical communication systems.

scholarly journals Monolithic optoelectronic integrated broadband optical receiver with graphene photodetectors

Nanophotonics ◽  
2017 ◽  
Vol 6 (6) ◽  
pp. 1343-1352 ◽  
Author(s):  
Chuantong Cheng ◽  
Beiju Huang ◽  
Xurui Mao ◽  
Zanyun Zhang ◽  
Zan Zhang ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Low Cost ◽  
Three Dimensional ◽  
Complementary Metal Oxide Semiconductor ◽  
Optical Signal ◽  
Optical Interconnect ◽  
Optical Receiver ◽  
Oxide Semiconductor ◽  
Experimental Realization ◽  
Operation Speed

AbstractOptical receivers with potentially high operation bandwidth and low cost have received considerable interest due to rapidly growing data traffic and potential Tb/s optical interconnect requirements. Experimental realization of 65 GHz optical signal detection and 262 GHz intrinsic operation speed reveals the significance role of graphene photodetectors (PDs) in optical interconnect domains. In this work, a novel complementary metal oxide semiconductor post-backend process has been developed for integrating graphene PDs onto silicon integrated circuit chips. A prototype monolithic optoelectronic integrated optical receiver has been successfully demonstrated for the first time. Moreover, this is a firstly reported broadband optical receiver benefiting from natural broadband light absorption features of graphene material. This work is a perfect exhibition of the concept of monolithic optoelectronic integration and will pave way to monolithically integrated graphene optoelectronic devices with silicon ICs for three-dimensional optoelectronic integrated circuit chips.

scholarly journals DIGITAL CONTROLLED OSCILLATOR (DCO) FOR ALL DIGITAL PHASE-LOCKED LOOP (ADPLL) – A REVIEW

2019 ◽  
Vol 82 (1) ◽  
Author(s):  
Florence Choong ◽  
Mamun Ibne Reaz ◽  
Mohamad Ibrahim Kamaruzzaman ◽  
Md. Torikul Islam Badal ◽  
Araf Farayez ◽  
...  
Keyword(s):  
Supply Voltage ◽  
Complementary Metal Oxide Semiconductor ◽  
Phase Locked Loop ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Process Technology ◽  
Chip Area ◽  
Digital Phase ◽  
Low Power Dissipation

Digital controlled oscillator (DCO) is becoming an attractive replacement over the voltage control oscillator (VCO) with the advances of digital intensive research on all-digital phase locked-loop (ADPLL) in complementary metal-oxide semiconductor (CMOS) process technology. This paper presents a review of various CMOS DCO schemes implemented in ADPLL and relationship between the DCO parameters with ADPLL performance. The DCO architecture evaluated through its power consumption, speed, chip area, frequency range, supply voltage, portability and resolution. It can be concluded that even though there are various schemes of DCO that have been implemented for ADPLL, the selection of the DCO is frequently based on the ADPLL applications and the complexity of the scheme. The demand for the low power dissipation and high resolution DCO in CMOS technology shall remain a challenging and active area of research for years to come. Thus, this review shall work as a guideline for the researchers who wish to work on all digital PLL.

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