scholarly journals Influence of the rapid thermal treatment of the gate dielectric on the parameters of integrated circuits of time devices

Doklady BGUIR ◽  
2020 ◽  
Vol 18 (3) ◽  
pp. 20-27
Author(s):  
V. A. Saladukha ◽  
V. A. Pilipenko ◽  
V. A. Gorushko
Keyword(s):  
Thermal Treatment ◽  
Integrated Circuits ◽  
Gate Dielectric

scholarly journals Reliability Express Control of the Gate Dielectric of Semiconductor Devices

2018 ◽  
Vol 9 (4) ◽  
pp. 308-313
Author(s):  
V. A. Solodukha ◽  
G. G. Chigir ◽  
V. A. Pilipenko ◽  
V. A. Filipenya ◽  
V. A. Gorushko
Keyword(s):  
Thermal Treatment ◽  
Integrated Circuits ◽  
Gate Dielectric ◽  
Semiconductor Devices ◽  
Silicon Wafers ◽  
Express Method ◽  
Running Time ◽  
Reliability Indicators ◽  
Initial Silicon ◽  
Free Running

The key element determining stability of the semiconductor devices is a gate dielectric. As its thickness reduces in the process of scaling the combined volume of factors determining its electrophysical properties increases. The purpose of this paper is development of the control express method of the error-free running time of the gate dielectric and study the influence of the rapid thermal treatment of the initial silicon wafers and gate dielectric on its reliability.The paper proposes a model for evaluation of the reliability indicators of the gate dielectrics as per the trial results of the test MDS-structures by means of applying of the ramp-increasing voltage on the gate up to the moment of the structure breakdown at various velocities of the voltage sweep with measurement of the IV-parameters. The proposed model makes it possible to realize the express method of the reliability evaluation of the thin dielectrics right in the production process of the integrated circuits.On the basis of this method study of the influence of the rapid thermal treatment of the initial silicon wafers of the KEF 4.5, KDB 12 wafers and formed on them by means of the pyrogenic oxidation of the gate dielectric for the error-free running time were performed. It is shown, that rapid thermal treatment of the initial silicon wafers with their subsequent oxidation results in increase of the error-free running time of the gate dielectric on average from 12.9 to 15.9 years (1.23 times greater). Thermal treatment of the initial silicon wafers and gate dielectric makes it possible to expand the error-free running time up to 25.2 years, i.e.1.89 times more, than in the standard process of the pyrogenic oxidation and 1.5 times more, than under application of the rapid thermal treatment of the initial silicon wafers only.

scholarly journals Application of Radiation-Thermal Treatment to Suppress Sensitivity of Silicon Microcircuits to Single Radiation Effects

2021 ◽  
Vol 8 (3) ◽  
pp. 99-103
Author(s):  
P. B. Lagov ◽  
◽  
A. S. Drenin ◽  
A. A. Meshcheryakov ◽  
N. A. Yudanov ◽  
...  
Keyword(s):  
Thermal Treatment ◽  
Integrated Circuits ◽  
Radiation Effects ◽  
Experimental Tests ◽  
High Energy ◽  
Particle Accelerators ◽  
Transfer Coefficients ◽  
Heavy Charged Particles ◽  
Equilibrium Charge ◽  
Technological Tool

The paper analyses the possibility to reduce the sensitivity of silicon integrated circuits (ICs) to single radiation effects by means of radiation-thermal treatment including irradiation in charged particle accelerators and subsequent low-temperature heat treatment. It is shown that reduction in sensitivity to single radiation effects is provided by formation of thermostable recombination centers in semiconductor IC structure in necessary concentrations. At the same time a decrease in primary photocurrent generated by heavy charged particles or high-energy protons, reduction in transfer coefficients of parasitic bipolar transistors forming thyristor structures, reduction in carrier avalanche multiplication coefficients at high electric field strengths can be provided. Radiationthermal treatment can be introduced in the manufacturing process of ICs of various classes at the end of the manufacturing cycle and does not require correction of the basic technology. A possible undesirable growth of inverse currents and preservation of values of other electrical parameters within acceptable values when using radiation-thermal treatment is provided by choosing optimal modes of irradiation and annealing which are established in the course of experimental tests. The calculated evaluation has shown that using radiation-thermal treatment in the technology of IC fabrication can provide a decrease in the effective collection length of non-equilibrium charge carriers generated under the influence of single radiation effects by at least 10 times which allows considering radiation-thermal treatment as an effective technological tool to suppress the sensitivity to single radiation effects.

Top-Gate ZnO Nanowire Transistors and Integrated Circuits with Ultrathin Self-Assembled Monolayer Gate Dielectric

Nano Letters ◽  
2011 ◽  
Vol 11 (12) ◽  
pp. 5309-5315 ◽  
Author(s):  
Daniel Kälblein ◽  
R. Thomas Weitz ◽  
H. Jens Böttcher ◽  
Frederik Ante ◽  
Ute Zschieschang ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Gate Dielectric ◽  
Zno Nanowire ◽  
Self Assembled Monolayer ◽  
Nanowire Transistors ◽  
Self Assembled

Extendibility of the PECVD Porogen Approach for ULK Materials

2007 ◽  
Vol 990 ◽  
Author(s):  
Olivier Gourhant ◽  
Vincent Jousseaume ◽  
Laurent Favennec ◽  
Aziz Zenasni ◽  
Patrick Maury ◽  
...  
Keyword(s):  
Dielectric Constant ◽  
Thermal Treatment ◽  
Integrated Circuits ◽  
Hybrid Film ◽  
Uv Curing ◽  
Post Treatment ◽  
Low Dielectric Constant ◽  
K Value ◽  
Organic Species ◽  
Low Dielectric

ABSTRACTThe increase of integrated circuits performances requires ultra-low dielectric constant (ULK) materials to minimize the drawbacks of miniaturization. Amorphous SiOCH are promising candidates for ULK materials as porosity can be introduced via a two steps elaboration. In a first step, organo-silicon species and organic species are co-deposited by PECVD. Then, a thermal annealing, alone or assisted by UV radiation, removes the organic labile phase and creates pore inclusions into the final material. In this work, the extendibility of this porogen approach is investigated in order to lower the dielectric constant. An increase of the porogen loading in hybrid film is studied by tuning the precursors ratio injected in the plasma gas feed. The increase of organic species amount is operated in order to create more pores sites. However, the post-treatment does not lead automatically to higher porosity. Actually, an increase of the porosity is observed only until a porogen loading limit and decreases above this limit. The shrinkage of the film during the post-treatment can explain this limitation. For high ratios of porogen, the film shrinkage increases drastically and leads to a decrease of the porosity finally created. At last, the link between porosity and dielectric constant is enlightened and a minimum in term of K value is reached with both post-treatments: dielectric constant of 2.1 and 2.3 are obtained using respectively thermal treatment and UV curing.

scholarly journals Structural-phase junctions in the system of Pt–Si during rapid thermal treatment

2020 ◽  
Vol 64 (2) ◽  
pp. 238-244
Author(s):  
U. A. Pilipenka ◽  
F. F. Komarov ◽  
V. A. Saladukha ◽  
V. A. Harushka
Keyword(s):  
Thermal Treatment ◽  
Integrated Circuits ◽  
Structural Phase ◽  
Phase System ◽  
Crystal Silicon ◽  
Temperature Range ◽  
Platinum Silicide ◽  
Double Phase ◽  
Time Period ◽  
Pt Films

In recent years the interest to silicides significantly rose relating to their huge potentialities as the material of the low-Ohm contacts and interconnections of metallization of the silicon integrated circuits. In view of this the necessity appeared to consider more extensively the thermal dynamic, electric and structural peculiarities of their formation. Purpose of the work was in investigation of influence of the rapid thermal treatment on the structural –phase junctions in the system of Pt–Si during formation of platinum silicide. As samples, the Pt films were used, 43.7 nm thick and applied on the substrates of the mono-crystal silicon KEF КЭФ 0.5 with orientation (111) by means of the magnetron sputtering of the platinum target with purity of 99.95 % on the unit MRS 603 with the cryogenic pumping to the pressure not worse, than 5 · 10–5 Pa. As the operating medium, argon was used, whose purity constituted 99.933 %. Rapid thermal treatment was performed in the nitrogen medium within the temperature range from 200 to 550 °С with a step of 50 °С and the time period of 7 s. The process of interaction of platinum with silicon during treatment of the Pt–Si system was evaluated by means of the analysis of the RBS spectra. It is demonstrated, that within the temperature range of 200 °С ≤ Т ≤ 300 °С during 7 s of the rapid thermal process on the boundary of the metal film with the substrate, formation takes place of the Pt2Si layer owing to diffusion of the Pt atoms into silicon via the layer of the growing silicide. The temperature Т = 300 °С is peculiar for the complete application of the Pt film during 7 s in process of the silicide formation of the single phase system of Pt2Si. At 350 °С ≤ Т < 450 °С formation is registered of the double phase system of Pt2Si → PtSi, starting from the inter-phase boundary of Si/Pt2Si predominantly owing to the opposite diffusion of the Si atoms into the layer of Pt2Si. The temperature of the rapid thermal treatment Т = 450 °С marks formation of the thermally stable balanced structure of PtSi along the entire silicide thickness, which is 50–100 °С lower and considerably more rapid, than during the long-term balanced thermal treatment.

scholarly journals Three-Dimensional TID Hardening Design for 14 nm Node SOI FinFETs

Eng ◽  
2021 ◽  
Vol 2 (4) ◽  
pp. 620-631
Author(s):  
Peng Lu ◽  
Can Yang ◽  
Yifei Li ◽  
Bo Li ◽  
Zhengsheng Han
Keyword(s):  
Integrated Circuits ◽  
Computer Aided Design ◽  
Gate Dielectric ◽  
Capture Rate ◽  
Three Dimensional ◽  
Silicon On Insulator ◽  
Threshold Voltage Shift ◽  
Space Applications ◽  
Effect Transistor ◽  
Aided Design

The fin field-effect transistor (FinFET) has been the mainstream technology on the VLSI platform since the 22 nm node. The silicon-on-insulator (SOI) FinFET, featuring low power consumption, superior computational power and high single-event effect (SEE) resistance, shows advantages in integrated circuits for space applications. In this work, a rad-hard design methodology for SOI FinFETs is shown to improve the devices’ tolerance against the Total Ionizing Dose (TID) effect. Since the fin height direction enables a new dimension for design optimization, a 3D Source/Drain (S/D) design combined with a gate dielectric de-footing technique, which has been readily developed for the 14 nm node FinFETs, is proposed as an effective method for SOI FinFETs’ TID hardening. More importantly, the governing mechanism is thoroughly investigated using fully calibrated technology computer-aided design (TCAD) simulations to guide design optimizations. The analysis demonstrates that the 3D rad-hard design can modulate the leakage path in 14 nm node n-type SOI FinFETs, effectively suppress the transistors’ sensitivity to the TID charge and reduce the threshold voltage shift by >2×. Furthermore, the rad-hard design can reduce the electric field in the BOX region and lower its charge capture rate under radiation, further improving the transistor’s robustness.

scholarly journals TCAD Simulation of the Doping-Less TFET with Ge/SiGe/Si Hetero-Junction and Hetero-Gate Dielectric for the Enhancement of Device Performance

Coatings ◽  
2020 ◽  
Vol 10 (3) ◽  
pp. 278 ◽  
Author(s):  
Tao Han ◽  
Hongxia Liu ◽  
Shupeng Chen ◽  
Shulong Wang ◽  
Haiwu Xie
Keyword(s):  
Integrated Circuits ◽  
Gate Dielectric ◽  
Field Effect Transistors ◽  
Source Region ◽  
Cutoff Frequency ◽  
Tunneling Current ◽  
Frequency Characteristics ◽  
Device Structure ◽  
Ultra Low Power ◽  
Current Switching

The device structure of DLTFET is optimized by the Silvaco TCAD software to solve the problems of lower on-state current and larger miller capacitance of traditional doping-less tunneling field effect transistors (DLTFETs), and the performance can be greatly improved. Different from the traditional DLTFETs, the source region and pocket region of the doping-less TFET with the Ge/SiGe/Si hetero-junction and hetero-gate dielectric (H-DLTFET), respectively, use the narrow band-gap semiconductor Ge and SiGe materials, and the channel and drain region both use the silicon material. The H-DLTFET device use the Ge/SiGe hetero-junction engineering to decrease the tunneling barrier width, increase the band-to-band tunneling current, and obtain the higher current switching ratio and ultra-low sub-threshold swing (SS). Besides, the gate dielectric under auxiliary gate uses the low-k dielectric SiO2 material, which can effectively reduce the miller capacitance and improve the capacitance and frequency characteristics. The on-state current, switching ratio, trans-conductance, output current, and output conductance values of H-DLTFET can be increased by two, two, one, one, and one order of magnitude when compared with the DLTFET, respectively. Meanwhile, the point SS and average SS, respectively, decrease from 13 mV/Dec and 31.6 mV/Dec to 5 mV/Dec and 14.3 mV/Dec, and the gate-drain capacitance decrease from 0.99 fF/μm to 0.1 fF/μm. Besides, the cutoff frequency and gain bandwidth product of H-DLTFET are much larger than that of DLTFET, which can be explained by the excellent DC characteristics. The above simulation results show that the H-DLTFET has the better frequency characteristics, so it is more suitable for applications of ultra-low-power integrated circuits.

scholarly journals Formation of a gate dielectric of nanometer thickness by rapid thermal treatment

Doklady BGUIR ◽  
2021 ◽  
Vol 19 (4) ◽  
pp. 103-112
Author(s):  
N. S. Kovalchuk ◽  
A. A. Omelchenko ◽  
V. A. Pilipenko ◽  
V. A. Solodukha ◽  
D. V. Shestovski
Keyword(s):  
Integrated Circuits ◽  
Silicon Oxide ◽  
Gate Dielectric ◽  
Active Regions ◽  
Nitrogen Atmosphere ◽  
Chemical Cleaning ◽  
Stage Process ◽  
Maximum Temperatures ◽  
Two Stages ◽  
Radio Corporation Of America

Investigations of the thickness and optical characteristics of thin SiO2 films obtained by one-, two-, or three-stage rapid thermal processing (RTP) at atmospheric pressure, pulses of 6, 12, and 20 s duration have been carried out. To obtain thin SiO2 films by the RTP method, N-type:Ph 4.5 Оhm/□ (100) silicon wafers were used as initial samples. The samples were preliminarily oxidized at 1000 °C of the obtained wet oxygen (SiO2 d = 100 nm), then the silicon oxide was completely removed in a solution of hydrofluoric acid, after which the wafers were subjected to chemical cleaning using the Radio Corporation of America (RCA) technology. Oxidation in a stationary oxygen atmosphere was carried out in one or two stages by heating the plates with a light pulse of different power up to maximum temperatures of 1035 – 1250 °C, as well as a three-stage process, where the final stage was annealing in a nitrogen atmosphere or in a forming gas (N2 97% + H2 3%). The characteristics of SiO2-Si barrier structures nitrided in N2, obtained by the RTP process by light fluxes with pulses of a second duration, were studied to improve the electrophysical parameters of gate oxides by the RTP method. It is of interest for integrated circuits (ICS) with a high density of the active regions of devices.

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