scholarly journals TCAD Simulation of the Doping-Less TFET with Ge/SiGe/Si Hetero-Junction and Hetero-Gate Dielectric for the Enhancement of Device Performance

Coatings ◽  
2020 ◽  
Vol 10 (3) ◽  
pp. 278 ◽  
Author(s):  
Tao Han ◽  
Hongxia Liu ◽  
Shupeng Chen ◽  
Shulong Wang ◽  
Haiwu Xie
Keyword(s):  
Integrated Circuits ◽  
Gate Dielectric ◽  
Field Effect Transistors ◽  
Source Region ◽  
Cutoff Frequency ◽  
Tunneling Current ◽  
Frequency Characteristics ◽  
Device Structure ◽  
Ultra Low Power ◽  
Current Switching

The device structure of DLTFET is optimized by the Silvaco TCAD software to solve the problems of lower on-state current and larger miller capacitance of traditional doping-less tunneling field effect transistors (DLTFETs), and the performance can be greatly improved. Different from the traditional DLTFETs, the source region and pocket region of the doping-less TFET with the Ge/SiGe/Si hetero-junction and hetero-gate dielectric (H-DLTFET), respectively, use the narrow band-gap semiconductor Ge and SiGe materials, and the channel and drain region both use the silicon material. The H-DLTFET device use the Ge/SiGe hetero-junction engineering to decrease the tunneling barrier width, increase the band-to-band tunneling current, and obtain the higher current switching ratio and ultra-low sub-threshold swing (SS). Besides, the gate dielectric under auxiliary gate uses the low-k dielectric SiO2 material, which can effectively reduce the miller capacitance and improve the capacitance and frequency characteristics. The on-state current, switching ratio, trans-conductance, output current, and output conductance values of H-DLTFET can be increased by two, two, one, one, and one order of magnitude when compared with the DLTFET, respectively. Meanwhile, the point SS and average SS, respectively, decrease from 13 mV/Dec and 31.6 mV/Dec to 5 mV/Dec and 14.3 mV/Dec, and the gate-drain capacitance decrease from 0.99 fF/μm to 0.1 fF/μm. Besides, the cutoff frequency and gain bandwidth product of H-DLTFET are much larger than that of DLTFET, which can be explained by the excellent DC characteristics. The above simulation results show that the H-DLTFET has the better frequency characteristics, so it is more suitable for applications of ultra-low-power integrated circuits.

SELF-CONSISTENT SIMULATION OF QUANTUM DOT FLASH MEMORY DEVICE WITH SiO2 AND HfO2 DIELECTRICS

2005 ◽  
Vol 04 (02) ◽  
pp. 171-178
Author(s):  
CHEE CHING CHONG ◽  
KAI HONG ZHOU ◽  
PING BAI ◽  
ER PING LI ◽  
GANESH S. SAMUDRA
Keyword(s):  
Quantum Dot ◽  
Flash Memory ◽  
Gate Dielectric ◽  
Tunneling Current ◽  
Memory Device ◽  
Device Structure ◽  
Dielectric Thickness ◽  
Silicon Quantum Dot ◽  
High K ◽  
Self Consistent

Flash memory structure in which a silicon quantum dot embedded in the gate dielectric region between the channel and the control gate is considered. A self-consistent simulation for such memory devices is performed and aims to understand the relationship between the device structure and the meaningful quantities, as required for an efficient device operation. In this study, both the traditional SiO2 and HfO2 high-k dielectrics are being explored, and their results are compared and contrasted. In particular, the superiority of HfO2 over the SiO2 is demonstrated through various interlocking investigations on the relationships between the tunneling current, dielectric thickness, barrier height, programming and retention times.

Fabrication and Characterization of Directly-Assembled ZnO Nanowire Field Effect Transistors with Polymer Gate Dielectrics

2007 ◽  
Vol 7 (11) ◽  
pp. 4101-4105
Author(s):  
Ahnsook Yoon ◽  
Woong-Ki Hong ◽  
Takhee Lee
Keyword(s):  
Dielectric Layer ◽  
Field Effect ◽  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Field Effect Transistors ◽  
Electrical Characterization ◽  
Electrical Characteristics ◽  
Zno Nanowire ◽  
Device Structure

We report the fabrication and electrical characterization of ZnO nanowire field effect transistors (FETs). Dielectrophoresis technique was used to directly align ZnO nanowires between lithographically prepatterned source and drain electrodes, and spin-coated polyvinylphenol (PVP) polymer thin layer was used as a gate dielectric layer in "top-gate" FET device configuration. The electrical characteristics of the top-gate ZnO nanowire FETs were found to be comparable to the conventional "bottom-gate" nanowire FETs with a SiO2 gate dielectric layer, suggesting the directly-assembled nanowire FET with a polymer gate dielectric layer is a useful device structure of nanowire FETs.

scholarly journals Design and Investigation of the Junction-Less TFET with Ge/Si0.3Ge0.7/Si Heterojunction and Heterogeneous Gate Dielectric

Electronics ◽  
2019 ◽  
Vol 8 (5) ◽  
pp. 476 ◽  
Author(s):  
Tao Han ◽  
Hongxia Liu ◽  
Shulong Wang ◽  
Shupeng Chen ◽  
Wei Li ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Computer Aided Design ◽  
Gate Dielectric ◽  
Dielectric Material ◽  
Source Region ◽  
Ultra Low Power ◽  
Narrow Bandgap ◽  
Order Of Magnitude ◽  
Drain Region ◽  
Aided Design

To improve the on-state current and reduce the miller capacitance of the conventional junction-less tunneling field effect transistor (JLTFET), the junction-less TFET with Ge/Si0.3Ge0.7/Si heterojunction and heterogeneous gate dielectric (H-JLTFET) is investigated by the Technology Computer Aided Design (TCAD) simulation in this paper. The source region uses the narrow bandgap semiconductor material germanium to obtain the higher on-state current; the gate dielectric adjacent to the drain region adopts the low-k dielectric material SiO2, which is considered to reduce the gate-to-drain capacitance effectively. Moreover, the gap region uses the Si0.3Ge0.7 material to decrease the tunneling distance. In addition, the effects of the device sizes, doping concentration and work function on the performance of the H-JLTFET are analyzed systematically. The optimal on-state current and switching ratio of the H-JLTFET can reach 6 µA/µm and 2.6 × 1012, which are one order of magnitude and four orders of magnitude larger than the conventional JLTFET, respectively. Meanwhile, the gate-to-drain capacitance, off-state current and power consumption of the H-JLTFET can be effectively suppressed, so it will have a great potential in future ultra-low power integrated circuit applications.

Improvement in the performance of graphene nanoribbon p-i-n tunneling field effect transistors by applying lightly doped profile on drain region

2017 ◽  
Vol 31 (31) ◽  
pp. 1750248 ◽  
Author(s):  
Ali Naderi
Keyword(s):  
Field Effect ◽  
Field Effect Transistors ◽  
Source Region ◽  
Cutoff Frequency ◽  
Graphene Nanoribbon ◽  
Doping Profile ◽  
Current Ratio ◽  
Doping Density ◽  
Consistent Solution ◽  
Drain Region

In this paper, an efficient structure with lightly doped drain region is proposed for p-i-n graphene nanoribbon field effect transistors (LD-PIN-GNRFET). Self-consistent solution of Poisson and Schrödinger equation within Nonequilibrium Green’s function (NEGF) formalism has been employed to simulate the quantum transport of the devices. In proposed structure, source region is doped by constant doping density, channel is an intrinsic GNR, and drain region contains two parts with lightly and heavily doped doping distributions. The important challenge in tunneling devices is obtaining higher current ratio. Our simulations demonstrate that LD-PIN-GNRFET is a steep slope device which not only reduces the leakage current and current ratio but also enhances delay, power delay product, and cutoff frequency in comparison with conventional PIN GNRFETs with uniform distribution of impurity and with linear doping profile in drain region. Also, the device is able to operate in higher drain–source voltages due to the effectively reduced electric field at drain side. Briefly, the proposed structure can be considered as a more reliable device for low standby-power logic applications operating at higher voltages and upper cutoff frequencies.

scholarly journals Ultra-Low Power and High-Throughput SRAM Design to Enhance AI Computing Ability in Autonomous Vehicles

Electronics ◽  
2021 ◽  
Vol 10 (3) ◽  
pp. 256
Author(s):  
Youngbae Kim ◽  
Shreyash Patel ◽  
Heekyung Kim ◽  
Nandakishor Yadav ◽  
Kyuwon Ken Choi
Keyword(s):  
Integrated Circuits ◽  
Power Consumption ◽  
Low Power ◽  
High Throughput ◽  
Autonomous Vehicles ◽  
Field Effect Transistors ◽  
State Of The Art ◽  
Electrical Performance ◽  
Large Area ◽  
Ultra Low Power

Power consumption and data processing speed of integrated circuits (ICs) is an increasing concern in many emerging Artificial Intelligence (AI) applications, such as autonomous vehicles and Internet of Things (IoT). Existing state-of-the-art SRAM architectures for AI computing are highly accurate and can provide high throughput. However, these SRAMs have problems that they consume high power and occupy a large area to accommodate complex AI models. A carbon nanotube field-effect transistors (CNFET) device has been reported as a potential candidates for AI devices requiring ultra-low power and high-throughput due to their satisfactory carrier mobility and symmetrical, good subthreshold electrical performance. Based on the CNFET and FinFET device’s electrical performance, we propose novel ultra-low power and high-throughput 8T SRAMs to circumvent the power and the throughput issues in Artificial Intelligent (AI) computation for autonomous vehicles. We propose two types of novel 8T SRAMs, P-Latch N-Access (PLNA) 8T SRAM structure and single-ended (SE) 8T SRAM structure, and compare the performance with existing state-of-the-art 8T SRAM architectures in terms of power consumption and speed. In the SRAM circuits of the FinFET and CNFET, higher tube and fin numbers lead to higher operating speed. However, the large number of tubes and fins can lead to larger area and more power consumption. Therefore, we optimize the area by reducing the number of tubes and fins without compromising the memory circuit speed and power. Most importantly, the decoupled reading and writing of our new SRAMs cell offers better low-power operation due to the stacking of device in the reading part, as well as achieving better readability and writability, while offering read Static Noise Margin (SNM) free because of isolated reading path, writing path, and greater pull up ratio. In addition, the proposed 8T SRAMs show even better performance in delay and power when we combine them with the collaborated voltage sense amplifier and independent read component. The proposed PLNA 8T SRAM can save 96%, while the proposed SE 8T SRAM saves around 99% in writing power consumption compared with the existing state-of-the-art 8T SRAM in FinFET model, as well as 99% for writing operation in CNFET model.

scholarly journals A Novel Dopingless Fin-Shaped SiGe Channel TFET with Improved Performance

2020 ◽  
Vol 15 (1) ◽  
Author(s):  
Shupeng Chen ◽  
Shulong Wang ◽  
Hongxia Liu ◽  
Tao Han ◽  
Haiwu Xie ◽  
...  
Keyword(s):  
High Efficiency ◽  
Physical Mechanism ◽  
Gate Dielectric ◽  
Cutoff Frequency ◽  
Subthreshold Swing ◽  
Gain Bandwidth ◽  
Ultra Low Power ◽  
Interface Characteristics ◽  
Capacitance Characteristics ◽  
Improved Performance

Abstract In this paper, a dopingless fin-shaped SiGe channel TFET (DF-TFET) is proposed and studied. To form a high-efficiency dopingless line tunneling junction, a fin-shaped SiGe channel and a gate/source overlap are induced. Through these methods, the DF-TFET with high on-state current, switching ratio of 12 orders of magnitude and no obvious ambipolar effect can be obtained. High κ material stack gate dielectric is induced to improve the off-state leakage, interface characteristics and the reliability of DF-TFET. Moreover, by using the dopingless channel and fin structure, the difficulties of doping process and asymmetric gate overlap formation can be resolved. As a result, the structure of DF-TFET can possess good manufacture applicability and remarkably reduce footprint. The physical mechanism of device and the effect of parameters on performance are studied in this work. Finally, on-state current (ION) of 58.8 μA/μm, minimum subthreshold swing of 2.8 mV/dec (SSmin), average subthreshold swing (SSavg) of 18.2 mV/dec can be obtained. With improved capacitance characteristics, cutoff frequency of 5.04 GHz and gain bandwidth product of 1.29 GHz can be obtained. With improved performance and robustness, DF-TFET can be a very attractive candidate for ultra-low-power applications.

scholarly journals A Doping-Less Tunnel Field-Effect Transistor with Si0.6Ge0.4 Heterojunction for the Improvement of the On–Off Current Ratio and Analog/RF Performance

Electronics ◽  
2019 ◽  
Vol 8 (5) ◽  
pp. 574 ◽  
Author(s):  
Tao Han ◽  
Hongxia Liu ◽  
Shupeng Chen ◽  
Shulong Wang ◽  
Wei Li
Keyword(s):  
Field Effect ◽  
Field Effect Transistor ◽  
Field Effect Transistors ◽  
Cutoff Frequency ◽  
Current Ratio ◽  
Germanium Content ◽  
Dielectric Thickness ◽  
Ultra Low Power ◽  
Effect Transistor ◽  
Rf Performance

In this paper, a novel doping-less tunneling field-effect transistor with Si0.6Ge0.4 heterojunction (H-DLTFET) is proposed using TCAD simulation. Unlike conventional doping-less tunneling field-effect transistors (DLTFETs), in H-DLTFETs, germanium and Si0.6Ge0.4 are used as source and channel materials, respectively, to provide higher carrier mobility and smaller tunneling barrier width. The energy band and charge carrier tunneling efficiency of the tunneling junction become steeper and higher as a result of the Si0.6Ge0.4 heterojunction. In addition, the effects of the source work function, gate oxide dielectric thickness, and germanium content on the performance of the H-DLTFET are analyzed systematically, and the below optimal device parameters are obtained. The simulation results show that the performance parameters of the H-DLTFET, such as the on-state current, on/off current ratio, output current, subthreshold swing, total gate capacitance, cutoff frequency, and gain bandwidth (GBW) product when Vd = 1 V and Vg = 2 V, are better than those of conventional silicon-based DLTFETs. Therefore, the H-DLTFET has better potential for use in ultra-low power devices.

scholarly journals Drain Current Model for Double Gate Tunnel-FETs with InAs/Si Heterojunction and Source-Pocket Architecture

Nanomaterials ◽  
2019 ◽  
Vol 9 (2) ◽  
pp. 181 ◽  
Author(s):  
Hongliang Lu ◽  
Bin Lu ◽  
Yuming Zhang ◽  
Yimen Zhang ◽  
Zhijun Lv
Keyword(s):  
Field Effect ◽  
Field Effect Transistors ◽  
Current Model ◽  
Tunneling Current ◽  
Drain Current ◽  
Device Structure ◽  
Band Engineering ◽  
Novel Device ◽  
Analytical Potential ◽  
Good Agreement

The practical use of tunnel field-effect transistors is retarded by the low on-state current. In this paper, the energy-band engineering of InAs/Si heterojunction and novel device structure of source-pocket concept are combined in a single tunnel field-effect transistor to extensively boost the device performance. The proposed device shows improved tunnel on-state current and subthreshold swing. In addition, analytical potential model for the proposed device is developed and tunneling current is also calculated. Good agreement of the modeled results with numerical simulations verifies the validation of our model. With significantly reduced simulation time while acceptable accuracy, the model would be helpful for the further investigation of TFET-based circuit simulations.

scholarly journals Design and Investigation of the High Performance Doping-Less TFET with Ge/Si0.6Ge0.4/Si Heterojunction

Micromachines ◽  
2019 ◽  
Vol 10 (6) ◽  
pp. 424 ◽  
Author(s):  
Tao Han ◽  
Hongxia Liu ◽  
Shupeng Chen ◽  
Shulong Wang ◽  
Wei Li
Keyword(s):  
Integrated Circuits ◽  
Field Effect ◽  
High Performance ◽  
Field Effect Transistor ◽  
Structure Parameters ◽  
Device Structure ◽  
Ultra Low Power ◽  
Order Of Magnitude ◽  
Effect Transistor ◽  
Channel Control

A high performance doping-less tunneling field effect transistor with Ge/Si0.6Ge0.4/Si heterojunction (H-DLTFET) is proposed in this paper. Compared to the conventional doping-less tunneling field effect transistor (DLTFET), the source and channel regions of H-DLTFET respectively use the germanium and Si0.6Ge0.4 materials to get the steeper energy band, which can also increase the electric field of source/channel tunneling junction. Meanwhile, the double-gate process is used to improve the gate-to-channel control. In addition, the effects of Ge content, electrode work functions, and device structure parameters on the performance of H-DLTFET are researched in detail, and then the above optimal device structure parameters can be obtained. Compared to the DLTFET, the simulation results show that the maximum on-state current, trans-conductance, and output current of H-DLTFET are all increased by one order of magnitude, whereas the off-state current is reduced by two orders of magnitude, so the switching ratio increase by three orders of magnitude. At the same time, the cut-off frequency and gain bandwidth product of H-DLTFET increase from 1.75 GHz and 0.23 GHz to 23.6 GHz and 4.69 GHz, respectively. Therefore, the H-DLTFET is more suitable for the ultra-low power integrated circuits.

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