scholarly journals A Comparative Review on ALU using CMOS and GDI techniques for Power Dissipation and Propagation Delay

IJOSTHE ◽  
2020 ◽  
Vol 7 (1) ◽  
pp. 4
Author(s):  
Rimjhim Saxena ◽  
Kiran Sharma
Keyword(s):  
Power Consumption ◽  
Power Dissipation ◽  
High Speed ◽  
Digital Signal ◽  
Propagation Delay ◽  
Logic Circuits ◽  
Compact Size ◽  
Comparative Review ◽  
Basic Functions ◽  
The One

Arithmetic and Logic Circuits are to be designed with less power, compact size, less propagation delay in this fast growing era of technology. Arithmetic operations are indispensable and the basic functions for any high speed low power applications like digital signal processing, microprocessors, image processing, etc. Consumption of power is the major issue in designing these circuits. Also the number of transistors required is also the one of the issues in designing the circuits. To minimize the transistors required in designing the circuits and to reduce the power consumption of the circuits, the authors have referred some techniques to overcome these problems in this paper. By reviewing all these techniques, the authors try to implement the GDI technique to reduce the power consumption and transistors count or the area required to design the circuits.

scholarly journals High Speed PSO Micro-Pipelined Adder

2020 ◽  
Vol 8 (5) ◽  
pp. 4073-4079
Keyword(s):  
Digital Signal Processor ◽  
Power Dissipation ◽  
High Speed ◽  
Continuous Monitoring ◽  
Digital Signal ◽  
Propagation Delay ◽  
Wearable Devices ◽  
Data Path ◽  
Processing Data ◽  
Cost Utilization

For continuous monitoring of individual wellbeing, wearable devices are indispensable. The limitations of cost, utilization of power, delay and restricted device measurements are the basic issues which should be dealt cautiously while designing these battery powered devices. The wearables use high-end processors dedicated for complicated signal processing. Data path plays a key role in every digital signal processor. Adder is the most widely used component in wearable technology. This work proposes a novel architecture for PS0 pipelined adder. The proposed adder is implemented in 65nm TSMC CMOS and its performance has been compared with state-of-art adders. The SPICE level simulations are performed on HSPICE using 65nm TSMC CMOS @ 1.2 V. All the designs have been simulated with extracted wire and layout parasitics. The proposed adder ensures the lowest propagation delay which is 79.33% less when compared to RCA and has a power dissipation of 0.225 mw which is 25.4 % less as compared to CLA. Besides, the proposed adder offers a benefit of having lower transistor count which is 49.6% less as compared to RCA.

scholarly journals High Speed, Low Area Exact Speculative Carry Look Ahead Adder using MGDI Technique

2019 ◽  
Vol 8 (6) ◽  
pp. 5090-5094
Keyword(s):  
Integrated Circuits ◽  
Power Consumption ◽  
High Speed ◽  
Digital Signal ◽  
Propagation Delay ◽  
Vital Role ◽  
Switching Behavior ◽  
Low Area ◽  
Look Ahead ◽  
Heating Up

The Exact Speculative Carry Look Ahead Adder using the Modified-GDI (Modified-Gate Diffusion Input) is suggested in this work. The delay, area and power tradeoff plays a vital role in VLSI. We already know that designs which are of CMOS style occupy more space may consume more power consumption. The switching behavior of the circuit cause the heating up of integrated circuits affects the working conditions of the functional unit. The adders are the main parts of several applications such as microprocessors, microcontrollers and digital signal processors and also in real time applications. Hence it is important to minimize the adder blocks to design a perfect processor. This work is proposed on a 16 bit carry look ahead adder is designed by using MGDI gate and 4T XOR gates and a speculator blocks. The proposed MGDI carry Look Ahead adder occupies 68% less area and the power consumption and the propagation delay also drastically reduces when compared to the conventional carry Look Ahead adder why because the number transistors drastically reduces from 1448 (Conventional) to 456 (Proposed CLA). The simulation results of the proposed design implemented in Xilinx.

scholarly journals Enhanced and Efficient Carry Select Adder with Minimal Delay

2021 ◽  
Author(s):  
G. Srividhya ◽  
T. Sivasakthi ◽  
R. Srivarshini ◽  
P. Varshaa ◽  
S. Vijayalakshmi
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
Digital Signal ◽  
Propagation Delay ◽  
Digital Signal Processors ◽  
Digital World ◽  
Carry Select Adder ◽  
Image Processors ◽  
Improved Model ◽  
Signal Processors

In today’s digital world, Arithmetic computations have been evolved as a core factor in digital signal processors, micro-controllers, and systems using arithmetic and logical operations such as adders, multipliers, image processors, and signal processors. One of the elements that play an important role in performing arithmetic calculations is an adder. Among many adders, the Carry Select Adder produces less propagation delay. However, there may be an increased delay, power consumption, and area required in the case of a normal Carry Select Adder. To overcome the mentioned drawbacks, an improved model of Carry Select Adder has been designed that uses Binary to Excess – 1 Converter. Instead of using multiple blocks of Ripple Carry Adders (RCAs), it is efficient and effective if one of the blocks is replaced with Binary to Excess – 1 Converter. As a result, we can achieve a high speed adder with minimal delay, minimal power, and reduced area.

scholarly journals DESIGN OF A LOW POWER FLIP-FLOP USING CMOS DEEP SUBMICRON TECHNOLOGY

2013 ◽  
pp. 260-264
Author(s):  
B. FRANCIS ◽  
Y. APPARAO ◽  
B. CHINNARAO
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
Short Pulse ◽  
Propagation Delay ◽  
Deep Submicron ◽  
Leakage Power ◽  
Flip Flop ◽  
Propagation Delays

This paper enumerates low power, high speed design of flip-flop having less number of transistors and only one transistor being clocked by short pulse train which is true single phase clocking (TSPC) flip-flop. Compared to Conventional flip-flop, it has 5 Transistors and one transistor clocked, thus has lesser size and lesser power consumption. It can be used in various applications like digital VLSI clocking system, buffers, registers, microprocessors etc. The analysis for various flip flops and latches for power dissipation and propagation delays at 0.13μm and 0.35μm technologies is carried out. The leakage power increases as technology is scaled down. The leakage power is reduced by using best technique among all run time techniques viz. MTCMOS. Thereby comparison of different conventional flip-flops, latches and TSPC flip-flop in terms of power consumption, propagation delays and product of power dissipation and propagation delay with SPICE simulation results is presented.

A LOW-POWER AND HIGH-SPEED D FLIP-FLOP USING A SINGLE LATCH

2002 ◽  
Vol 11 (01) ◽  
pp. 51-55
Author(s):  
ROBERT C. CHANG ◽  
L.-C. HSU ◽  
M.-C. SUN
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
Operating Frequency ◽  
Flip Flop ◽  
Lower Power ◽  
Simulation Results ◽  
Hspice Simulation

A novel low-power and high-speed D flip-flop is presented in this letter. The flip-flop consists of a single low-power latch, which is controlled by a positive narrow pulse. Hence, fewer transistors are used and lower power consumption is achieved. HSPICE simulation results show that power dissipation of the proposed D flip-flop has been reduced up to 76%. The operating frequency of the flip-flop is also greatly increased.

Simulation and Analysis of different CMOS Full Adders for Delay Optimisation

2021 ◽  
Vol 9 (9) ◽  
pp. 66-70
Author(s):  
Nakul C. Kubsad
Keyword(s):  
Power Dissipation ◽  
High Speed ◽  
Digital Signal ◽  
Full Adder ◽  
Digital Signal Processors ◽  
Transmission Gate ◽  
Logical Operations ◽  
Recent Advancement ◽  
Voltage Swing ◽  
Signal Processors

Abstract: Full adder circuit is one among the fundamental and necessary digital part. The full adder is be a part of microprocessors, digital signal processors etc. It's needed for the arithmetic and logical operations. Full adder design enhancements are necessary for recent advancement. The requirement of an adder cell is to provide high speed, consume low power and provide high voltage swing. This paper analyses and compares 3 adders with completely different logic designs (Conventional, transmission gate & pseudo NMOS) for transistor count, power dissipation and delay. The simulation is performed in Cadence virtuoso tool with accessible GPDK – 180nm kit. Transmission gate full adder has sheer advantage of high speed, fewer space and also it shows higher performance in terms of delay. Keywords: Delay, power dissipation, voltage, transistor sizing.

scholarly journals Design and Analysis of 32-bit Reverse Converter based on low power Parallel Prefix Adder

2019 ◽  
Vol 9 (1) ◽  
pp. 3028-3031
Keyword(s):  
Low Power ◽  
High Speed ◽  
Digital Signal ◽  
Number System ◽  
Residue Number System ◽  
Propagation Delay ◽  
Main Role ◽  
Reverse Conversion ◽  
Reverse Converter ◽  
Parallel Prefix

The Residue Number System (RNS) based reverse converter can play as main role in Parallel arithmetic operations of Digital Signal Processing (DSP) applications and VLSI technologies. Normally, by the use of carry adders, the reverse conversion design gives high delay and high power consumption. Due to resolve of above problem, the design of reverse converter is proposed by the use of familiar high speed (less propagation delay) Parallel Prefix - Kogge Stone Adder (PP- KSA). This paper describes the design of 32-bit Reverse converter with regular PP-KSA and proposed MUX (Multiplex) logic of PP-KSA with Hybrid Modular Parallel Prefix structure (HMPE) separately. In addition to that, the performance of that designs are analysed based on area, delay and power independently. The Performance results of proposed MUX logic of PP-KSA Reverse converter design yields low power than the other design which uses the regular PP-KSA. The simulation and synthesis effects can be done in Xilinx ISE 14.2i tool.

scholarly journals Subthreshold Region based Linear Feedback Shift Register

2019 ◽  
Vol 8 (6S2) ◽  
pp. 817-821
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
System Level ◽  
Linear Feedback ◽  
Portable Devices ◽  
Subthreshold Region ◽  
Flip Flop ◽  
Ultra Low Power

Growing demand for portable devices and fast increases in complexity of chip cause power dissipation is an important parameter. Power consumption and dissipation or generations of more heat possess a restriction in the direction of the integration of more transistors. Several methods have been proposed to reduce power dissipation from system level to device level. Subthreshold circuits are widely used in more advanced applications due to ultra low-power consumption. The present work targets on construction of linear feedback shift registers (LFSR) in weak inversion region and their performance observed in terms of parameters like power delay product (PDP). In CMOS circuits subthreshold region of operation allows a low-power for ample utilizations but this advantage get with the penalty of flat speed. For the entrenched and high speed applications, improving the speed of subthreshold designs is essential. To enhance this, operate the devices at maximum current over capacitance. LFSR architectures build with various types of D flip flop and XOR gate circuits are analyzed. Circuit level Simulation is carried out using 130 nm technologies.

scholarly journals IMPLEMENTATION OF HIGH SPEED-LOW POWER TRUNCATION ERROR TOLERANT ADDER

2015 ◽  
pp. 239-244
Author(s):  
SYAM KUMAR NAGENDLA ◽  
K. MIRANJI
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Critical Path ◽  
Processing System ◽  
Digital Signal ◽  
Signal Processing System ◽  
Speed Performance ◽  
Power Delay Product ◽  
Dsp Systems

Now a Days in modern VLSI technology different kinds of errors are invitable. A new type of adder i.e. error tolerant adder(ETA) is proposed to tolerate those errors and to attain low power consumption and high speed performance in DSP systems. In conventional adder circuit, delay is mainly certified to the carry propagation chain along the critical path, from the LSB to MSB. If the carry propagation can be eliminated by the technique proposed in this paper, a great improvement in speed performance and power consumption is achieved. By operating shifting and addition in parallel, the error tolerant adder tree compensates for the truncation errors. To prove the feasibility of the ETA, normal addition operation present in the DFT or DCT algorithm is replaced by the proposed addition arithmetic and the experimental results are shown. In this paper we propose error tolerant Adder (ETA). In the view of DSP applications the ETA is able to case the strict restriction on accuracy, speed performance and power consumption when compared to the conventional Adders, the proposed one provides 76% improvement in power-delay product such a ETA plays a key role in digital signal processing system that can tolerate certain amount of errors.

scholarly journals About Possibilities of the Probabilistic Form of Information Representation in Military Computing Devices

2021 ◽  
Vol 19 (4) ◽  
pp. 111-117
Author(s):  
N. E. Sapozhnikov ◽  
V. G. Zolotykh ◽  
A. S. Zakharov
Keyword(s):  
Signal Processing ◽  
Power Consumption ◽  
Digital Signal Processing ◽  
High Speed ◽  
Rapid Development ◽  
Practical Importance ◽  
Digital Signal ◽  
Developed Countries ◽  
Computing Systems ◽  
Complex Problems

At present, digital signal processing involves enormous amounts of computations with large-bit arrays, which are carried out in real time. In connection with the need to solve more and more complex problems, constantly growing requirements are imposed on the main parameters of digital processors (speed, reliability, power consumption, etc.), which determine the computing capabilities of systems with digital signal processing. In turn, the rapid development of microelectronics, its successes make it possible to create more and more high-performance computing systems, which makes it possible to solve more and more complex problems, including in the military sphere. The production of the latest information technology means is a technological task that can be solved exclusively by economically developed countries. Bringing domestic microelectronics to the current world level requires significant investments. Therefore, the study and research of discrete nodes and devices is of the direct practical importance. When developing promising computers, new technological approaches should be applied: minimizing power consumption, maintaining modularity and high computational density within a single node, creating high-speed data transmission with the lowest delays, creating an efficient storage system, and choosing the best types of memory. One of such possible approaches is the use of a non-positional form of information presentation in computing systems for national and military purposes. This gives a number of advantages, the main ones of which are: a decrease (by orders of magnitude) in the hardware volume of computing devices, an increase in the speed of calculations, an increase in the noise immunity of communication channels. To use the above method, it is proposed to include a probabilistic arithmetic device in the information processing device that performs basic arithmetic operations (addition, multiplication, exponentiation, subtraction, division), which are performed without the use of additional algorithms and mechanisms, in contrast to “classical" digital representation of binary information, where all operations are performed on the basis of the addition operation.

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