scholarly journals Investigation of Solder Joint Encapsulant Materials for Defect Mitigation

2020 ◽  
Vol 33 (1) ◽  
pp. 20-27
Author(s):  
Sue Teng ◽  
Cherif Guirguis ◽  
Gnyaneshwar Ramakrishna ◽  
Hien Ly
Keyword(s):  
Form Factor ◽  
Solder Joint ◽  
High Speed ◽  
Bulk Solder ◽  
Solder Paste ◽  
Application Process ◽  
Product Platforms ◽  
Fine Pitch ◽  
Bottom Side ◽  
Separation Failure

As Cisco’s next-generation products continue to push the trends of higher signal speeds and increased functional density, the need for advanced PCB structures, such as Via-in-Pad Plated Over (VIPPO) and backdrill, and high-speed memory is becoming more mainstream across product platforms.  Furthermore, as these high-speed memory technologies are being driven by consumer applications, the form factor and interconnect pitches continue to shrink to meet the demands of the mobile device market.  The use of these advanced PCB structures, like VIPPO and VIPPO with backdrill, within the BGA footprints, particularly for the fine pitch patterns, have been found to result in BGA solder separation defects at the bulk solder to IMC interface upon a 2nd reflow, e.g. during top-side reflow for bottom-side components or during rework of an adjacent BGA.1  In some cases, this solder separation failure mode has also been identified with buried vias under the BGA pad or even without the presence of VIPPO or any vias under the BGA pad. 2.3 Additionally, these small memory components have been experiencing high occurrences of head-in-pillow (HIP) defects even though the overall package warpage over the reflow profile is < ~3mils. This paper will therefore focus on the mitigation of these solder joint defects resulting from SMT assembly with the use of solder joint encapsulant materials to provide enhanced adhesion strength for the solder joints.  Leveraging existing test vehicles that are known to induce the aforementioned solder joint defects, 2 different solder joint encapsulant or epoxy flux materials are evaluated in terms of the application process, assembly integrity and compatibility with Cisco’s production solder paste materials and SMT processes.

A First Room Temperature Stable and Jetable Solder Joint Encapsulant Adhesive

2011 ◽  
Vol 2011 (1) ◽  
pp. 000509-000515 ◽  
Author(s):  
Mary Liu ◽  
Wusheng Yin
Keyword(s):  
Solder Joint ◽  
High Speed ◽  
Room Temperature ◽  
Low Cost ◽  
White Paper ◽  
Solder Paste ◽  
Fine Pitch ◽  
Increasing Demand ◽  
The Right ◽  
Device Miniaturization

With the increasing demand of device miniaturization, high speed, more memory, more function, low cost, and more flexibility in device design and manufacturing chain, YINCAE has published a white paper on a first individual solder joint encapsulant which can eliminate underfilling process with at least five times solder joint increase and provide more flexibility for fine pitch and high density application. In order to meet the demand of manufacturing of high speed and low cost, YINCAE has invented a room temperature stable and jettable solder joint encapsulant adhesive – SMT 266. The invention of SMT 266 has allowed our customers to have more flexibility in their high-speed production line such as worry free on the work life of adhesive and workable jetting process. After being used in the customer field for a few years, the implementation of SMT266 has been approved improving the process yield, eliminating voids and cracks in solder joint, eliminating head-in-pillow issue for large component during lead free reflow process. The results from thermal cycling test indicated that the first failure cycles using SMT266 is high up to 6000 cycles, at least 4000 – 5000 cycles higher than other processes. The pull strength is 1.5 times higher than using solder paste plus underfilling process. All reliability data implied encapsulating each individual solder joint is the right direction to move toward. The enforcement mechanism will be discussed in our paper.

The Benefits of Flux-Coated Solder Preforms in a QFN Assembly Process

2015 ◽  
Vol 2015 (1) ◽  
pp. 000827-000832
Author(s):  
Brandon Judd ◽  
Maria Durham
Keyword(s):  
Mechanical Properties ◽  
Form Factor ◽  
Solder Joint ◽  
Circuit Board ◽  
Electrical Performance ◽  
Solder Paste ◽  
Assembly Process ◽  
Circuit Board Assembly ◽  
Difficult Challenge ◽  
Small Form Factor

The use of bottom terminated components (BTCs) such as quad-flat no-leads (QFNs) has become commonplace in the circuit board assembly world. This package offers several benefits including its small form factor, its excellent thermal and electrical performance, easy PCB trace routing, and reduced lead inductance. These components are generally attached to PWBs PCBs via solder paste. The design of these components with the large thermal pad, along with the tendency of solder paste to outgas during reflow from the volatiles in the flux, creates a difficult challenge in terms of voiding control within the solder joint. Voiding can have a serious effect on the performance of these components, including the mechanical properties of the joint as well as spot overheating. Solder preforms with a flux coating can be added to the solder paste to help reduce voiding. This study will focus on the benefits of utilizing solder preforms with modern flux coatings in conjunction with solder paste to help reduce voiding under QFNs, as well as the design and process parameters which provide optimal results.

scholarly journals Reliability Study of Solder Paste Alloy for the Improvement of Solder Joint at Surface Mount Fine-Pitch Components

Materials ◽  
2014 ◽  
Vol 7 (12) ◽  
pp. 7706-7721 ◽  
Author(s):  
Mohd Rahman ◽  
Noor Zubir ◽  
Raden Leuveano ◽  
Jaharah Ghani ◽  
Wan Mahmood
Keyword(s):  
Solder Joint ◽  
Solder Paste ◽  
Reliability Study ◽  
Surface Mount ◽  
Fine Pitch

Developments in Stencil Printing Technology for 0.3mm Pitch CSP Assembly

2011 ◽  
Vol 2011 (1) ◽  
pp. 000502-000508 ◽  
Author(s):  
Mark Whitmore ◽  
Clive Ashmore
Keyword(s):  
Form Factor ◽  
Area Ratio ◽  
Transfer Efficiency ◽  
Solder Paste ◽  
Assembly Process ◽  
Next Generation ◽  
Stencil Printing ◽  
Printing Process ◽  
Fine Pitch ◽  
Solder Pastes

As electronics assemblies continue to shrink in form factor, forcing designers towards smaller components with decreasing pitches, the Surface Mount assembly process is becoming increasingly challenged. A new “active” squeegee printing process has been developed to assist in the stencil printing of solder pastes for next generation ultra fine pitch components such as 0.3mm pitch CSP’s. Results indicate that today’s accepted stencil area ratio rules, which govern solder paste transfer efficiency can be significantly pushed to extend stencil printing process capabilities to stencil apertures having area ratios as low as 0.4. Such a breakthrough will allow the printing of ultra fine pitch components and additionally will assist with heterogeneous assembly concerns, to satisfy up and coming mixed technology demands.

Analysis of Solder Paste Release in Fine Pitch Stencil Printing Processes

1999 ◽  
Vol 121 (3) ◽  
pp. 169-178 ◽  
Author(s):  
G. Rodriguez ◽  
D. F. Baldwin
Keyword(s):  
High Speed ◽  
Flip Chip ◽  
Imaging System ◽  
Main Process ◽  
Print Quality ◽  
Solder Paste ◽  
Release Process ◽  
Stencil Printing ◽  
Fine Pitch ◽  
Analytical Approaches

Advanced electronics packaging technologies such as chip scale packages, fine pitch ball grid arrays, and flip chip are pushing solder paste stencil printing to the limit. In order to achieve solder print deposits of the sizes required for emerging electronic packaging technology, a rigorous understanding of the process is required. This paper seeks to expand our understanding of the physical characteristics of stencil printing specifically focusing on the solder paste release process based on experimental and analytical approaches. First, designed experiments were conducted to identify the main process variables affecting final print quality. An in-situ measurement system using a high speed imaging system monitored the solder paste release process. Based on experimental observations, different modes of solder paste release and their corresponding mechanisms were identified. A model was developed to predict print quality for fine pitch applications. The proposed model was experimentally verified showing good agreement with measured values for fine pitch and very fine pitch printing. It was found that the cohesive and adhesive forces acting on the paste tend to govern the release process rather than the viscous and inertial forces.

Stencil Printing Process Guidelines for 0.3mm Pitch Chip Scale Packages

2013 ◽  
Vol 2013 (1) ◽  
pp. 000569-000573
Author(s):  
Mark Whitmore ◽  
Jeff Schake ◽  
Clive Ashmore
Keyword(s):  
Form Factor ◽  
Area Ratio ◽  
Solder Paste ◽  
Assembly Process ◽  
Aperture Size ◽  
Stencil Printing ◽  
Printing Process ◽  
Fine Pitch ◽  
New Process ◽  
Electronic Assemblies

With the form factor of electronic assemblies continuing to shrink, designers are being forced towards smaller, more complex components with decreasing interconnection pitches. As a consequence, the Surface Mount assembly process is becoming increasingly challenged. For the stencil printing process, todays accepted stencil area ratio rules, (which dictate what can or cannot be printed), need to be significantly pushed to extend the printing process for next generation ultra -fine pitch components. With aperture geometries shrinking, anything which can influence solder paste transfer efficiency has to be considered. New process technologies such as ultrasonic squeegees have emerged in recent years to assist the process with some degree of success. However, something which is often overlooked in terms of stencil design influence is that a square shaped aperture, size for size, has a volume which is 21.5% than its circular counterpart. In a process where quite literally every solder particle that can be printed is becoming significant then this fact can be utilized to the process engineer's advantage. In this paper, the merits of stencil aperture shape, in conjunction with ultrasonic squeegees are investigated with the purpose of developing stencil printing guidelines for ultra-fine pitch components such as 0.3mm pitch CSP's.

Reballing/Rebumping Ultra-Fine Pitch Packages Less Than 0.5 mm Pitch for FA

2014 ◽  
Author(s):  
Bob Wettermann
Keyword(s):  
Solder Joint ◽  
Failure Analysis ◽  
Joint Strength ◽  
Semiconductor Devices ◽  
X Ray ◽  
Fine Pitch ◽  
Manual Methods

Abstract As the pitch and package sizes of semiconductor devices have shrunk and their complexity has increased, the manual methods by which the packages can be re-bumped or reballed for failure analysis have not kept up with this miniaturization. There are some changes in the types of reballing preforms used in these manual methods along with solder excavation techniques required for packages with pitches as fine as 0.3mm. This paper will describe the shortcomings of the previous methods, explain the newer methods and materials and demonstrate their robustness through yield, mechanical solder joint strength and x-ray analysis.

scholarly journals Influence of tool edge form factor and cutting parameters on milling performance

2021 ◽  
Vol 13 (4) ◽  
pp. 168781402110090
Author(s):  
Xuefeng Zhao ◽  
Hao Qin ◽  
Zhiguo Feng
Keyword(s):  
Form Factor ◽  
Simulation Model ◽  
Cutting Force ◽  
Surface Quality ◽  
High Speed ◽  
Orthogonal Cutting ◽  
Cutting Temperature ◽  
Tool Edge ◽  
Drag Finishing ◽  
Edge Preparation

Tool edge preparation can improve the tool life, as well as cutting performance and machined surface quality, meeting the requirements of high-speed and high-efficiency cutting. In general, prepared tool edges could be divided into symmetric or asymmetric edges. In the present study, the cemented carbide tools were initially edge prepared through drag finishing. The simulation model of the carbide cemented tool milling steel was established through Deform software. Effects of edge form factor, spindle speed, feed per tooth, axial, and radial cutting depth on the cutting force, the tool wear, the cutting temperature, and the surface quality were investigated through the orthogonal cutting simulation. The simulated cutting force results were compared to the results obtained from the orthogonal milling experiment through the dynamometer Kistler, which verified the simulation model correctness. The obtained results provided a basis for edge preparation effect along with high-speed and high effective cutting machining comprehension.

scholarly journals Reliability Evaluation of Fan-Out Type 3D Packaging-On-Packaging

Micromachines ◽  
2021 ◽  
Vol 12 (3) ◽  
pp. 295
Author(s):  
Pao-Hsiung Wang ◽  
Yu-Wei Huang ◽  
Kuo-Ning Chiang
Keyword(s):  
Finite Element ◽  
Thermal Cycling ◽  
Glass Substrate ◽  
High Speed ◽  
Coefficient Of Thermal Expansion ◽  
Three Dimensional ◽  
Design Parameters ◽  
Time To Failure ◽  
Wafer Level ◽  
Fine Pitch

The development of fan-out packaging technology for fine-pitch and high-pin-count applications is a hot topic in semiconductor research. To reduce the package footprint and improve system performance, many applications have adopted packaging-on-packaging (PoP) architecture. Given its inherent characteristics, glass is a good material for high-speed transmission applications. Therefore, this study proposes a fan-out wafer-level packaging (FO-WLP) with glass substrate-type PoP. The reliability life of the proposed FO-WLP was evaluated under thermal cycling conditions through finite element simulations and empirical calculations. Considering the simulation processing time and consistency with the experimentally obtained mean time to failure (MTTF) of the packaging, both two- and three-dimensional finite element models were developed with appropriate mechanical theories, and were verified to have similar MTTFs. Next, the FO-WLP structure was optimized by simulating various design parameters. The coefficient of thermal expansion of the glass substrate exerted the strongest effect on the reliability life under thermal cycling loading. In addition, the upper and lower pad thicknesses and the buffer layer thickness significantly affected the reliability life of both the FO-WLP and the FO-WLP-type PoP.

scholarly journals Study on the Reliability of Sn–Bi Composite Solder Pastes with Thermosetting Epoxy under Thermal Cycling and Humidity Treatment

Crystals ◽  
2021 ◽  
Vol 11 (7) ◽  
pp. 733
Author(s):  
Lu Liu ◽  
Songbai Xue ◽  
Ruiyang Ni ◽  
Peng Zhang ◽  
Jie Wu
Keyword(s):  
Solder Joint ◽  
Thermal Cycling ◽  
Composite Solder ◽  
Solder Joints ◽  
Solder Paste ◽  
Epoxy System ◽  
Mechanical Reinforcement ◽  
Microstructure Observation ◽  
Temperature And Humidity ◽  
Thermosetting Epoxy

In this study, a Sn–Bi composite solder paste with thermosetting epoxy (TSEP Sn–Bi) was prepared by mixing Sn–Bi solder powder, flux, and epoxy system. The melting characteristics of the Sn–Bi solder alloy and the curing reaction of the epoxy system were measured by differential scanning calorimeter (DSC). A reflow profile was optimized based on the Sn–Bi reflow profile, and the Organic Solderability Preservative (OSP) Cu pad mounted 0603 chip resistor was chosen to reflow soldering and to prepare samples of the corresponding joint. The high temperature and humidity reliability of the solder joints at 85 °C/85% RH (Relative Humidity) for 1000 h and the thermal cycle reliability of the solder joints from −40 °C to 125 °C for 1000 cycles were investigated. Compared to the Sn–Bi solder joint, the TSEP Sn–Bi solder joints had increased reliability. The microstructure observation shows that the epoxy resin curing process did not affect the transformation of the microstructure. The shear force of the TSEP Sn–Bi solder joints after 1000 cycles of thermal cycling test was 1.23–1.35 times higher than the Sn–Bi solder joint and after 1000 h of temperature and humidity tests was 1.14–1.27 times higher than the Sn–Bi solder joint. The fracture analysis indicated that the cured cover layer could still have a mechanical reinforcement to the TSEP Sn–Bi solder joints after these reliability tests.

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