The Dissimilar Self-Alignment Characteristics of Smaller Passive Components in the Length and Width Directions

Motivation: As passive components’ size gets smaller, quality rejects due to overhang and misalignment after the reflow appear more frequently. This situation is partly because the pass-fail criterion is set based on the offset concerning the component dimensions. Therefore, understanding the self-alignment characteristics of electronic components becomes very critical for surface-mount assembly yield. This research investigates the dissimilarity of self-alignment in the length and width directions. Approach: To avoid the argument of sample to sample variations, data are collected from 81 printed circuit boards (PCB) and 182,250 assembled components. Within a PCB, 25 different solder paste printing offset locations and 81 component placement offset settings are implemented. Component-placement positions before and after the reflow are monitored. The results are compared to identify different component sizes’ self-alignment characteristics in the length and width directions. Key findings: The misalignment of smaller passive components, e.g., R0402M(0.40 mm × 0.20 mm), is worse than the larger component under the identical solder paste printing and component placement conditions. Furthermore, the self-alignment characteristic in the length direction of these passive components, e.g., R0402M, to R1005M (1.00 mm × 0.50 mm) is superior to that of width direction. The observations are not consistent with the results found in earlier research that reported on larger components, e.g., C0402M(0.40 mm × 0.20 mm), to C3216M(3.20 mm × 1.50 mm).

High Density RDL Technologies for Panel Level Packaging of Embedded Dies

The ongoing miniaturization and functional heterogeneity in electronics packaging are pushing the demand for advanced substrate technologies. Highly integrated, advanced multi-chip packaging solutions combine application, logic and computing dies with memory or components for power management in a single package. A solution to achieve low fabrication costs is the close embedding of thin dies in IC Substrates based on large formats (600 x 600 mm²), known from PCB fabrication. In a consortium of partners from industry and research advanced technologies for Panel Level Packaging (PLP) are developed. This paper will show the development of 5µm L/S RDL routing density and chips with 50µm bump pitch. Here, the 6x6 mm² dies are symmetrically embedded into an organic laminate matrix. A PCB core (100µm thickness) with very low coefficient of thermal expansion (CTE) containing laser cut cavities is used, acting as a frame layer. Besides mechanical and handling stability, the usage of such a frame offers the advantage of pre-integrating additional features like local fiducials, through vias or power lines by conventional PCB processes. Within that frame, the dies are embedded by lamination of an organic build-up film with 25µm thickness equal to bump height. The chip contacts are then opened without the need of any micro via formation. Here a strong focus is set on RIE etching of the polymer material. Highly accurate measurement of the real die position is essential for the following processing. The formation of the redistribution layer (RDL) is done in a semi-additive process (SAP) utilizing sputtering technique and direct imaging (LDI). To achieve the fine pitch demands, an adaptive imaging process is applied. Therefore, a newly developed LDI machine is used to write structures in a 7µm photoresist. This exposure also combines the measurement data of the real die position and the adaption of the exposure artwork, in order to achieve highest registration quality.

Miniaturized Stacked Die QFN for Tire Pressure Monitoring System Applications

Tire Pressure Monitoring Systems (TPMS) are electronic wireless systems that monitor and report air pressure inside pneumatic tires in real time. An example of a TPMS module integrated with the valve stem and showing the typical tire mounting location is shown in Figure 1. For their safety and fuel economy benefits, starting with the mid-2000's, active TPMS were mandated on many vehicles worldwide. The NHTS estimates that there are approximately 23,000 accidents and 535 fatalities annually involving tire underinflation and blowouts [1]. The use of TPMS has been shown to result in improved fuel economy and therefore reduced carbon emissions [2]. TPMS in passenger vehicles was mandated in the US as of Sept. 1, 2007 under the TREAD Act, in the European Union as of Nov. 1, 2012 and in South Korea as of Jan.1, 2013. Countries like Russia, Indonesia, the Philippines, Israel, Malaysia, Turkey and many others soon followed [3]. The first TPMS systems were large and bulky with a significant electronics content [4]. Since that time TPMS electronics have gotten more energy efficient and form factors have come down dramatically. This paper will outline an effort to miniaturize an existing 1.0 mm pitch, 7x7x2.2 mm body size 24 lead QFN (Quad Flat No Leads) TPMS down to a 4x4x1.98 mm body size QFN with 0.5 mm pitch that would still meet automotive AEC Grade 1 reliability requirements. The original 7x7 mm three die QFN package consisted of an ASIC, a pressure sensor and an accelerometer. This miniaturization led to many technical challenges at both the package and board level. This paper will primarily address the board level reliability (BLR) challenges encountered due to the large silicon to package ratio along with the 50% reduction in pitch. Through a series of test vehicles with variables such as QFN leadframe surface finish, lead shape and size, wettable flank (WF) technology and anchors pads, the BLR was successfully improved to the point where it met application requirements.

Reliability and Performance of Wafer Level Fan Out Package for Automotive Radar

Embedded wafer level ball grid array (eWLB) or FO-WLP (Fan-out wafer-level packaging) is investigated as a package for MMICs (Monolithic Microwave Integrated Circuit) for automotive radar applications in the 77GHz range. Special focus is put on the thermo-mechanical performance to achieve automotive quality targets. The typical fatigue modes “solder ball fatigue” and “copper fatigue”, evolving during thermo-mechanical stress like cycling on board will be discussed. Simulation as well as experimental preparation results for typical fatigue levels are given. In addition, several influencing parameters are listed and rated regarding their effectiveness. The theoretical framework why solder ball fatigue is the only failure mode causing electrical failure is provided. The impact of different thermo-mechanically driven fatigue modes is discussed. The two important parameters to be considered for the functionality of the Radar system are RF (Radio Frequency) and thermal performance. For elaborating the RF performance with present fatigue modes, the phase shift between different channels and pads is analyzed by full-wave EM (Electromagnetic) simulation. It is found that for fatigue levels up to 90% the phase shift stays below specification for single fatigue modes and may approach specification only for an unlikely combination of all 90% fatigue modes. For assessing the thermal performance with present fatigue modes, thermal simulation as well as thermal measurements are used. Assuming 50% degradation in average for all thermal balls, an increase in RTH of up to about 30% is seen. On average for all thermal measurements, the deviation between measurement and simulation is within ±1°C.

Tin Whisker Formation on Small Outline Transistors Assembled Using Bismuth-Containing Lead-Free Solder Alloys After Long-Term Ambient Temperature, High Humidity Storage Part 3: In-Depth Characterization and Mechanisms

With the introduction of environmental legislation such as the Restriction of Hazardous Substances (RoHS), lead (Pb)-free materials have made their way into the electronics manufacturing industry. One issue that has emerged is that Pb-free solder alloys can initiate and grow tin whiskers under specific conditions. These whiskers are thin, highly conductive filaments which have the potential to grow and can cause field failures in many applications. Most concerning with respect to tin whiskering are high reliability applications such as aerospace, automotive, and medical. Bismuth (Bi) is being considered for inclusion in solder alloys to replace the current industry standard (SAC 305) and provide improved thermomechanical and vibration reliability. In this paper, we discuss whisker formation of several Bi-bearing alloys after long-term (12,000 hours), ambient high humidity (25°C/85% RH) storage. Three alloys containing Bi, in addition to SAC 305 (Sn-3.0Ag-0.5Cu), were considered. These alloys were Violet (Sn-2.25Ag-0.5Cu-6.0Bi), Sunflower (Sn-0.7Cu-7.0Bi), and Senju (Sn-2.0Ag-0.7Cu-3.0Bi). The boards were fabricated with electroless nickel immersion gold (ENIG) and immersion tin (ImmSn) finishes and populated with parts having Cu and Fe42Ni alloy leads and chip parts, with half of assemblies cleaned and half cleaned and contaminated with low levels of NaCl. This paper is the third in a series of three in which we share more in-depth characterization of features of interest from the small outline transistor (SOT) inspection. Discussion regarding the role of Bi in the overall stress state of the joint will also be provided.

Aerosol Jet Direct Writing Polymer-Thick-Film Resistors for Printed Electronics

To improve performance and reduce size of printed-circuit board (PCB) in electronics industry, embedding discrete components within a board substrate has been an effective approach by reducing solder joints and their associated impedance mismatching, inductive reactance, etc. With its unique capabilities for non-contact precision material deposition, the Aerosol Jet® direct-write technology has been enabling additive manufacturing of fine-feature electronics conformally onto flexible substrates of complicated shapes. The CAD/CAM controlled relative motions between substrate and print head allows convenient adjustment of the pattern and pile height of deposited material at a given ink volumetric deposition rate. To date in the printed electronics industry, additively printing embedded polymer-thick-film (PTF) resistors has mostly been done with screen printing using carbon-based paste inks. Here we demonstrate results of Aerosol Jet® printed PTF resistors of resistance values ranging from ~50 W to > 1 kW, adjustable (among several variable parameters) by the number of stacked layers (or print passes with each pass depositing a fixed amount of ink) between contact pads of around 1 mm apart with footprint line typically < 0.3 mm. In principle, any ink material that can be atomized into fine droplets of 1 to 5 microns can be printed with the Aerosol Jet® system. However, the print quality such as line edge cleanliness can significantly influenced by ink rheology which involves solvent volatility, solids loading, and so on. Our atomizable carbon ink was made by simply diluting a screen printing paste with a compatible solvent of reasonable volatility, which can be cured at temperatures below 200 oC. We show that Aerosol Jet® printed overlapping lines can be stacked to large pile height (to reduce the resistance value) without significant increase of line width, which enables fabricating embedded resistors with adjustable resistance values in a limited footprint space.

Edgebond and Edgefill Induced Loading Effect on Large WLCSP Thermal Cycling Performance

Various external load conditions affecting components on electronic devices and modules are constant factors, which need to be considered for the component long-term reliability. Recently, to enhance the high stress component thermo-mechanical cycling performance, various types and configuration using edgebond and edgefill technology are introduced and tested. These applications induce a multi-axis loading condition, which alter the degradation mechanism and failure location during thermal cycling, which need closer investigation. In this study, high stress 12x12mm2 wafer level chip scale packages (WLCSP) were selected and subject to thermal cycling with full-edgebond, dot-edgebond and edgefill adhesive, which improves the characteristic lifecycle numbers base on the configurations, but altered the failure location due to different stress conditions. The -40 to 125oC thermal cycling profile revealed localized degradation per configuration during thermal cycling, showed a shift of the crack propagation path, based on full-edgebond, dot-edgebond and edgefill adhesive sample conditions. Through these series of observation, the interconnect thermal cycling degradation mechanisms are able to be explained. The correlation between the stress condition and microstructure are presented and discussed based on Electron backscattered diffraction (EBSD) analysis.

Impact of Conformal Coating Induced Stress on Wafer Level Chip Scale Package Thermal Cycling Performance

Conformal coating is commonly used for harsh environment to protect electronics from moisture and chemical contaminants. But the stresses imparted by the conformal coating can cause degradation to the package thermal cycle performance. Full coverage of the component with conformal coating material can prevent potential corrosion induced degradation but imply a local compression stress during thermal cycling, resulting a different thermal cycling performance compared to non-coated components. In this study, 8x8mm2 wafer level chip scale packages (WLCSP) were subjected to 5% NaCl aqueous spray test with and without full conformal coating, then thermal cycled from -40ºC to +125ºC. Weibull reliability statistics indicated that fully conformal coated components experience characteristic life cycle number reduction from 404 cycles to 307 cycles, a 24% lifetime reduction, comparing to no conformal coated, no salt spray test applied components. The correlation between crack propagation and localized recrystallization were compared in a series of cross section analyses using polarized imaging and electro-backscattered diffraction, which revealed that the conformal coating induced a z-axis tension and compression strain during thermal cycling, resulting in an accelerated degradation at the solder interconnect. Linear Laser profilometer measurements showed that fully conformal coated samples experienced a higher z-axis height displacement change relative to non-conformal coated samples when exposed to 125 °C with 10 minutes dwell. To prevent this z-axis strain a reworkable edgebond adhesive was applied with full conformal coating configuration, which demonstrate an increase of characteristic lifecycle number to 2783 cycles, suggesting that the mitigation of the z-axis strain can vastly enhance the thermal cycling performance.

Periodic Pulse Plating of Mid-Aspect Ratio Printed Circuit Boards for Enhanced Productivity

ABSTRACT Pulse plating of copper has typically found use in the plating of very difficult, high aspect ratio printed circuit boards. Its ability to provide throwing power deep within through holes with aspect ratios as high as 30:1 is well established. This technology has long been thought of as a high technology, high cost, specialty process applicable only to high end products. This paper will discuss the advantages that pulse plating offers over conventional DC copper plating in high volume production applications for panels with aspect ratios of up to 12:1. These advantages are reduced plating time, increased throughput, and reduced plated copper thickness on the panel surface while meeting minimum in-hole copper thickness requirements.

Investigation of Solder Joint Encapsulant Materials for Defect Mitigation

As Cisco’s next-generation products continue to push the trends of higher signal speeds and increased functional density, the need for advanced PCB structures, such as Via-in-Pad Plated Over (VIPPO) and backdrill, and high-speed memory is becoming more mainstream across product platforms. Furthermore, as these high-speed memory technologies are being driven by consumer applications, the form factor and interconnect pitches continue to shrink to meet the demands of the mobile device market. The use of these advanced PCB structures, like VIPPO and VIPPO with backdrill, within the BGA footprints, particularly for the fine pitch patterns, have been found to result in BGA solder separation defects at the bulk solder to IMC interface upon a 2nd reflow, e.g. during top-side reflow for bottom-side components or during rework of an adjacent BGA.1 In some cases, this solder separation failure mode has also been identified with buried vias under the BGA pad or even without the presence of VIPPO or any vias under the BGA pad. 2.3 Additionally, these small memory components have been experiencing high occurrences of head-in-pillow (HIP) defects even though the overall package warpage over the reflow profile is < ~3mils. This paper will therefore focus on the mitigation of these solder joint defects resulting from SMT assembly with the use of solder joint encapsulant materials to provide enhanced adhesion strength for the solder joints. Leveraging existing test vehicles that are known to induce the aforementioned solder joint defects, 2 different solder joint encapsulant or epoxy flux materials are evaluated in terms of the application process, assembly integrity and compatibility with Cisco’s production solder paste materials and SMT processes.