Vulnerabilities of Secure and Reliable Low-Power Embedded Systems and Their Analysis Methods

2014 ◽  
pp. 102-122
Author(s):  
Norbert Druml ◽  
Manuel Menghin ◽  
Christian Steger ◽  
Armin Krieg ◽  
Andreas Genser ◽  
...  
Keyword(s):  
Embedded Systems ◽  
Power Consumption ◽  
Low Power ◽  
Mobile Devices ◽  
Development Process ◽  
Supply Voltage ◽  
Personal Data ◽  
Low Power Design ◽  
Fault Attacks ◽  
Wide Range

Due to the increase in popularity of mobile devices, it has become necessary to develop a low-power design methodology in order to build complex embedded systems with the ability to minimize power usage. In order to fulfill power constraints and security constraints if personal data is involved, test and verification of a design's functionality are imperative tasks during a product's development process. Currently, in the field of secure and reliable low-power embedded systems, issues such as peak power consumption, supply voltage variations, and fault attacks are the most troublesome. This chapter presents a comprehensive study over design analysis methodologies that have been presented in recent years in literature. During a long-lasting and successful cooperation between industry and academia, several of these techniques have been evaluated, and the identified sensitivities of embedded systems are presented. This includes a wide range of problem groups, from power and supply-related issues to operational faults caused by attacks as well as reliability topics.

scholarly journals Low Power Implementation of Linear Feedback Shift Registers

2019 ◽  
Vol 8 (2) ◽  
pp. 2375-2379
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Low Power Design ◽  
Pattern Generation ◽  
Optimization Techniques ◽  
Shift Register ◽  
Linear Feedback Shift Register ◽  
Linear Feedback ◽  
Wide Range ◽  
Feedback Shift Register

This paper describes low power design and implementation of Linear Feedback Shift Register (LFSR). The easiness in implementation and simple operation of Linear Feedback Shift Register have made it fit into a wide range of digital systems design. Since random pattern generation, data encryption and decryption play a major role in communication systems, the LFSR comes into view for developing the patterns for these applications. As the need increases day after day, simple and high-performance design of LFSR is required. As power consumption of the device being an important factor in the VLSI circuits, it has to be reduced by including power optimization techniques in the designs. Pulsed Latch is a popular technique of reducing power consumption which uses Pulsed Latches instead of flip-flops. As latches have lesser number of circuit elements compared to flip-flops, the area is also minimized. By implementing this pulsed latch technique, the linear feedback shift register can be designed with low power and area. The design entry is done in VHDL code and implemented using Cadence tool. In Cadence, Nclaunch, RTL Complier and Encounter tools are used for simulation, synthesis and implementation. With this method, the power reduction is achieved up to 41.99%

Efficient Instruction and Data Caching for High Performance Embedded Processors

1970 ◽  
pp. 9
Author(s):  
A. Ferrerón Labari ◽  
D. Suárez Gracia ◽  
V. Viñals Yúfera
Keyword(s):  
Embedded Systems ◽  
Power Consumption ◽  
Low Power ◽  
Interconnection Networks ◽  
High Performance ◽  
Critical Issue ◽  
Content Management ◽  
Structure Design ◽  
Portable Devices ◽  
On Chip

In the last years, embedded systems have evolved so that they offer capabilities we could only find before in high performance systems. Portable devices already have multiprocessors on-chip (such as PowerPC 476FP or ARM Cortex A9 MP), usually multi-threaded, and a powerful multi-level cache memory hierarchy on-chip. As most of these systems are battery-powered, the power consumption becomes a critical issue. Achieving high performance and low power consumption is a high complexity challenge where some proposals have been already made. Suarez et al. proposed a new cache hierarchy on-chip, the LP-NUCA (Low Power NUCA), which is able to reduce the access latency taking advantage of NUCA (Non-Uniform Cache Architectures) properties. The key points are decoupling the functionality, and utilizing three specialized networks on-chip. This structure has been proved to be efficient for data hierarchies, achieving a good performance and reducing the energy consumption. On the other hand, instruction caches have different requirements and characteristics than data caches, contradicting the low-power embedded systems requirements, especially in SMT (simultaneous multi-threading) environments. We want to study the benefits of utilizing small tiled caches for the instruction hierarchy, so we propose a new design, ID-LP-NUCAs. Thus, we need to re-evaluate completely our previous design in terms of structure design, interconnection networks (including topologies, flow control and routing), content management (with special interest in hardware/software content allocation policies), and structure sharing. In CMP environments (chip multiprocessors) with parallel workloads, coherence plays an important role, and must be taken into consideration.

A Very Low Power Quadrature VCO with Modified Current-Reuse and Back-Gate Coupling Topology

2017 ◽  
Vol 26 (11) ◽  
pp. 1750184 ◽  
Author(s):  
Qiuzhen Wan ◽  
Jun Dong ◽  
Hui Zhou ◽  
Fei Yu
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Phase Noise ◽  
Tuning Range ◽  
Supply Voltage ◽  
Voltage Controlled Oscillator ◽  
Back Gate ◽  
Current Reuse ◽  
Quadrature Vco ◽  
In Series

In this paper, a very low power modified current-reused quadrature voltage-controlled oscillator (QVCO) is proposed with the back-gate coupling technique for the quadrature signal generation. By stacking switching transistors in series like a cascode, the modified current-reused QVCO can be constructed in a totem-pole manner to reuse the dc biasing current and lower the power consumption. By utilizing the back-gates of switching transistors as coupling terminals to achieve the quadrature outputs, the back-gate coupled QVCO improves the phase noise and reduces the power consumption compared to the conventional coupling transistor based topology. Together with the modified current-reuse and back-gate coupling techniques, the proposed QVCO can operate at reduced supply voltage and power consumption while maintaining remarkable circuit performance in terms of low phase noise and wide tuning range. With a dc power of 1.6[Formula: see text]mW under a 0.8[Formula: see text]V supply voltage, the simulation results show the tuning range of the QVCO is from 2.36 to 3.04[Formula: see text]GHz as the tuning voltage is varied from 0.8 to 0.0[Formula: see text]V. The phase noise is [Formula: see text]118.3[Formula: see text]dBc/Hz at 1[Formula: see text]MHz offset frequency from the carrier frequency of 2.36[Formula: see text]GHz and the corresponding figure-of-merit of the QVCO is [Formula: see text]183.7[Formula: see text]dBc/Hz.

Green Semicondoctor Design Techniques and Challanges

2011 ◽  
pp. 404-411
Author(s):  
Somesh Rajain ◽  
Chetan Shingala ◽  
Ekata Mehul
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Management ◽  
Human Life ◽  
Semiconductor Industry ◽  
Low Power Design ◽  
Clock Gating ◽  
Consumer Device ◽  
Carbon Dioxide Co2 ◽  
Design Techniques

The large emission of Carbon dioxide (CO2) is not only affecting our ecology but also affecting human life. In schools, offices, factory and crowded railway/bus stations i.e crowded places with insufficient ventilations CO2 affects human life most. In a closed environment like school, If CO2 level starts raising above 700 parts per million (ppm) people will feel objectionable body odors and as it increase further people will feel very uncomfortable, dizzy and have headache etc. Our goal is to reduce CO2 emission and lower global warming. In Semiconductor Industry as the digital technology grows, the functionality of our electronics devices (For example: - Mobile phone, PC’s, home appliances etc) is constantly improves and mean while the demand for electronic devices to be more environment friendly is increasing. So we have to design systems with Low power consumption to curtail down green house gas emission as well as low power design are also a requirement of today’s market. The usage of mobile device in all kinds of applications is increasing day by day. These applications and corresponding devices also have their power requirements. The demand for mobile consumer device has made the power management the number one consideration in today‘s system design. To increase battery life, system chip designer needs to adopt an aggressive power management technique which includes multi voltage Design Island, power gating, dynamic voltage, frequency scaling, clock gating etc in the system. Adding all these greatly complicates the verification for the chip. Normally the designer neglects the implementation of power saving techniques due to the tradeoff between power reduction and verification costs. The costs become more important in terms of business, which leads to more power consumption. Those details can still be implemented provided we use right kind of tools & techniques that are also combined with design experience. In this chapter the focus is to firstly describe low power design techniques, its verification challenges and its solutions followed by the case study. It also guides for the selection of programmable device & RTL Core design criteria. To make green electronics devices we have to design system with low power design techniques.

Low Power Considerations in Ubiquitous Computing

2010 ◽  
pp. 158-174
Author(s):  
Robert Tesch ◽  
Ashok Kumar ◽  
Jamie Mason ◽  
Dania Alvarez ◽  
Mario Di’Mattia ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Ubiquitous Computing ◽  
Reducing Power ◽  
Low Power Design ◽  
Power Budget ◽  
Computing Systems ◽  
Research Directions ◽  
Design Considerations ◽  
Battery Technology

Majority of the devices that are used in ubiquitous computing are expected to be as small as possible, be able to perform as many computations as possible, and transmit the results to another device or computer. Such expectations in performance put a pressure on the power budget of such devices. It is a well-known fact that the advances in battery technology are much slower and cannot keep up with the performance demands of tiny gadgets unless new methods of designing and managing hardware and software are developed and used. This chapter will introduce the motivation for low power design considerations by discussing the power limitations of ubiquitous computing devices. Then the chapter will discuss the research directions that are being pursued in literature for reducing power consumption and increasing efficiency of ubiquitous computing systems.

scholarly journals A Low-Power High-Data-Transmission Multi-Lead ECG Acquisition Sensor System

Sensors ◽  
2019 ◽  
Vol 19 (22) ◽  
pp. 4996 ◽  
Author(s):  
Liang-Hung Wang ◽  
Wei Zhang ◽  
Ming-Hui Guan ◽  
Su-Ya Jiang ◽  
Ming-Hui Fan ◽  
...  
Keyword(s):  
Low Power ◽  
Clinical Diagnosis ◽  
Medical Staff ◽  
Supply Voltage ◽  
Sampling Rate ◽  
Low Power Design ◽  
Sensor System ◽  
Acquisition System ◽  
Ecg Signal ◽  
Acquisition Device

This study presents a low-power multi-lead wearable electrocardiogram (ECG) signal sensor system design that can simultaneously acquire the electrocardiograms from three leads, I, II, and V1. The sensor system includes two parts, an ECG test clothing with five electrode patches and an acquisition device. Compared with the traditional 12-lead wired ECG detection instrument, which limits patient mobility and needs medical staff assistance to acquire the ECG signal, the proposed vest-type ECG acquisition system is very comfortable and easy to use by patients themselves anytime and anywhere, especially for the elderly. The proposed study incorporates three methods to reduce the power consumption of the system by optimizing the micro control unit (MCU) working mode, adjusting the radio frequency (RF) parameters, and compressing the transmitted data. In addition, Huffman lossless coding is used to compress the transmitted data in order to increase the sampling rate of the acquisition system. It makes the whole system operate continuously for a long period of time and acquire abundant ECG information, which is helpful for clinical diagnosis. Finally, a series of tests were performed on the designed wearable ECG device. The results have demonstrated that the multi-lead wearable ECG device can collect, process, and transmit ECG data through Bluetooth technology. The ECG waveforms collected by the device are clear, complete, and can be displayed in real-time on a mobile phone. The sampling rate of the proposed wearable sensor system is 250 Hz per lead, which is dependent on the lossless compression scheme. The device achieves a compression ratio of 2.31. By implementing a low power design on the device, the resulting overall operational current of the device is reduced by 37.6% to 9.87 mA under a supply voltage of 2.1 V. The proposed vest-type multi-lead ECG acquisition device can be easily employed by medical staff for clinical diagnosis and is a suitable wearable device in monitoring and nursing the off-ward patients.

Low-Power and Reference-Less Data and Clock Recovery Circuit for Visible Light Receivers

2018 ◽  
Author(s):  
Ming-Cheng Liu ◽  
Paul C.-P. Chao ◽  
Soh Sze Khiong
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Visible Light ◽  
Low Voltage ◽  
Supply Voltage ◽  
Clock And Data Recovery ◽  
Optical Receiver ◽  
Clock Recovery ◽  
Cmos Process ◽  
Rf Receiver

In this paper a low power all-digital clock and data recovery (ADCDR) with 1Mhz frequency has been proposed. The proposed circuit is designed for optical receiver circuit on the battery-less photovoltaic IoT (Internet of Things) tags. The conventional RF receiver has been replaced by the visible light optical receiver for battery-less IoT tags. With this proposed ADCDR a low voltage, low power consumption & tiny IoT tags can be fabricated. The proposed circuit achieve the maximum bandwidth of 1MHz, which is compatible with the commercial available LED and light sensor. The proposed circuit has been fabricated in TSMC 0.18um 1P6M standard CMOS process. Experimental results show that the power consumption of the optical receiver is approximately 5.58uW with a supply voltage of 1V and the data rate achieves 1Mbit/s. The lock time of the ADCDR is 0.893ms with 3.31ns RMS jitter period.

scholarly journals Encoding Schemes for Reducing Transition Activity and Power Consumption in VLSI Interconnects-A Review

2018 ◽  
Vol 7 (3.1) ◽  
pp. 34
Author(s):  
Vithyalakshmi. N ◽  
Nagarajan P ◽  
Ashok Kumar.N ◽  
Vinoth. G.S
Keyword(s):  
Energy Dissipation ◽  
Power Consumption ◽  
Low Power ◽  
Vlsi Design ◽  
Low Power Design ◽  
System Size ◽  
Vlsi Circuits ◽  
Portable Devices ◽  
Dynamic Power ◽  
Transition Activity

Low power design is a foremost challenging issue in recent applications like mobile phones and portable devices. Advances in VLSI technology have enabled the realization of complicated circuits in single chip, reducing system size and power utilization. In low power VLSI design energy dissipation has to be more significant. So to minimize the power consumption of circuits various power components and their effects must be identified. Dynamic power is the major energy dissipation in micro power circuits. Bus transition activity is the major source of dynamic power consumption in low power VLSI circuits. The dynamic power of any complex circuits cannot be estimated by the simple calculations. Therefore this paper review different encoding schemes for reduction of transition activity and power dissipation. 

A LOW POWER CRYOGENIC CMOS ROIC DESIGN FOR 512 × 512 IRFPA

2013 ◽  
Vol 22 (10) ◽  
pp. 1340033 ◽  
Author(s):  
HONGLIANG ZHAO ◽  
YIQIANG ZHAO ◽  
YIWEI SONG ◽  
JUN LIAO ◽  
JUNFENG GENG
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Integrated Circuit ◽  
High Performance ◽  
Supply Voltage ◽  
Cmos Technology ◽  
High Gain ◽  
Readout Integrated Circuit ◽  
Chip Area ◽  
Operating Modes

A low power readout integrated circuit (ROIC) for 512 × 512 cooled infrared focal plane array (IRFPA) is presented. A capacitive trans-impedance amplifier (CTIA) with high gain cascode amplifier and inherent correlated double sampling (CDS) configuration is employed to achieve a high performance readout interface for the IRFPA with a pixel size of 30 × 30 μm2. By optimizing column readout timing and using two operating modes in column amplifiers, the power consumption is significantly reduced. The readout chip is implemented in a standard 0.35 μm 2P4M CMOS technology. The measurement results show the proposed ROIC achieves a readout rate of 10 MHz with 70 mW power consumption under 3.3 V supply voltage from 77 K to 150 K operating temperature. And it occupies a chip area of 18.4 × 17.5 mm2.

Research of Low Power Design Strategy Based on IEEE 1801 Unified Power Format

2014 ◽  
Vol 981 ◽  
pp. 21-24
Author(s):  
Shu Ping Cui ◽  
Chuang Xie
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Circuit Design ◽  
High Power ◽  
Low Power Design ◽  
Design Strategy ◽  
Design Flow ◽  
Battery Life ◽  
Electronic Systems ◽  
High Power Consumption

Power consumption is becoming an increasingly important aspect of circuit design. High power consumption can lead to high machine temperature, short battery life which makes laptop electronics difficult to be widely used. IEEE 1801 Unified Power Format (UPF) is designed to express power intent for electronic systems and components .This paper first introduces the power principles, puts forward the approaches to reduce power consumption according to UPF, and then demonstrates the Synopsys design flow based on UPF, finally gives the power report and makes a conclusion.

Sign in / Sign up

Export Citation Format

Share Document