An Effective CS-BP Algorithm for 2-D DOA Estimation

2011 ◽  
Vol 128-129 ◽  
pp. 62-65
Author(s):  
Yu Yan An ◽  
Sen Sen Bai
Keyword(s):  
Frequency Modulation ◽  
Sampling Rate ◽  
Doa Estimation ◽  
Bp Algorithm ◽  
Basis Pursuit ◽  
Two Dimensional ◽  
Digital Converter ◽  
Analog To Digital ◽  
High Sampling Rate ◽  
Simulation Results

The bandwidth of the direction of arrival (DOA) estimation requires high sampling rate which extends the current analog to digital converter capacity. The paper presents an effective basis pursuit (BP) algorithm based on compressive sensing (CS) signals, which is called CS-BP algorithm, for two-dimensional (2-D) DOA estimation of Linear Frequency Modulation (LFM ). The simulation results verified that the method can effectively reduce the sampling data, and improve DOA estimation performance and efficiency.

scholarly journals An Optical Analog-to-Digital Converter with Enhanced ENOB Based on MMI-Based Phase-Shift Quantization

Photonics ◽  
2021 ◽  
Vol 8 (2) ◽  
pp. 52
Author(s):  
Yue Liu ◽  
Jifang Qiu ◽  
Chang Liu ◽  
Yan He ◽  
Ran Tao ◽  
...  
Keyword(s):  
Phase Shift ◽  
Multimode Interference ◽  
Analog To Digital Converter ◽  
Effective Number ◽  
Digital Converter ◽  
Analog To Digital ◽  
Mmi Coupler ◽  
Simulation Results ◽  
Optical Analog ◽  
Optical Quantization

An optical analog-to-digital converter (OADC) scheme with enhanced bit resolution by using a multimode interference (MMI) coupler as optical quantization is proposed. The mathematical simulation model was established to verify the feasibility and to investigate the robustness of the scheme. Simulation results show that 20 quantization levels (corresponding to 4.32 of effective number of bits (ENOB)) are realized by using only 6 channels, which indicates that the scheme requires much fewer quantization channels or modulators to realize the same amount of ENOB. The scheme is robust and potential for integration.

scholarly journals Effects of ADC Nonlinearity on the Spurious Dynamic Range Performance of Compressed Sensing

2014 ◽  
Vol 2014 ◽  
pp. 1-6 ◽  
Author(s):  
Rongzong Kang ◽  
Pengwu Tian ◽  
Hongyi Yu
Keyword(s):  
Compressed Sensing ◽  
Dynamic Range ◽  
Dynamic Performance ◽  
Digital Converter ◽  
Analog To Digital ◽  
Sensing System ◽  
Spurious Free Dynamic Range ◽  
Simulation Results ◽  
The Impact ◽  
Free Dynamic

Analog-to-information converter (AIC) plays an important role in the compressed sensing system; it has the potential to significantly extend the capabilities of conventional analog-to-digital converter. This paper evaluates the impact of AIC nonlinearity on the dynamic performance in practical compressed sensing system, which included the nonlinearity introduced by quantization as well as the circuit non-ideality. It presents intuitive yet quantitative insights into the harmonics of quantization output of AIC, and the effect of other AIC nonlinearity on the spurious dynamic range (SFDR) performance is also analyzed. The analysis and simulation results demonstrated that, compared with conventional ADC-based system, the measurement process decorrelates the input signal and the quantization error and alleviate the effect of other decorrelates of AIC, which results in a dramatic increase in spurious free dynamic range (SFDR).

scholarly journals A 10-bit 150MS/s Pipelined ADC with 2.5bit Gain Stage for High Frequency Applications

2019 ◽  
Vol 8 (10) ◽  
pp. 883-886
Keyword(s):  
Power Supply ◽  
High Frequency ◽  
Sampling Rate ◽  
High Accuracy ◽  
Pipelined Adc ◽  
Effective Number ◽  
Digital Converter ◽  
Analog To Digital ◽  
Computational Burden ◽  
Gain Stage

This paper proposes a 10-bit pipelined Analog to Digital Converter (ADC) which incorporates various techniques for lesser power and higher performance. The proposed method reduces the computational burden while comparing to the modified Monte-Carlo (MC) method. Pipelined ADC has N number of stages, it has higher resolution and higher frequency of conversion while comparing to other ADCs. The proposed ADC employs five 2.5bit gain stages; instead of 1.5bit gain stages for high accuracy. This method is implemented in the Tanner Software with the Generic 250nm library at a maximum power supply of 5V. The maximum frequency attained is 150MHz; and the ADC exhibits a SNR of 61.96dB. It also attains a 10bits as effective number of bits at the maximum sampling rate.

scholarly journals Highly Accurate Multi-Invariance ESPRIT for DOA Estimation with a Sparse Array

2019 ◽  
Vol 2019 ◽  
pp. 1-7
Author(s):  
Chen Gu ◽  
Hong Hong ◽  
Yusheng Li ◽  
Xiaohua Zhu ◽  
Jin He
Keyword(s):  
Doa Estimation ◽  
Invariance Property ◽  
Two Dimensional ◽  
Sparse Array ◽  
Half Wavelength ◽  
Vector Sensors ◽  
Matrix Blocks ◽  
Simulation Results ◽  
Non Gaussian ◽  
Array Geometry

This paper proposes a multi-invariance ESPRIT-based method for estimation of 2D direction (MIMED) of multiple non-Gaussian monochromatic signals using cumulants. In the MIMED, we consider an array geometry containing sparse L-shaped diversely polarized vector sensors plus an arbitrarily-placed single polarized scalar sensor. Firstly, we define a set of cumulant matrices to construct two matrix blocks with multi-invariance property. Then, we develop a multi-invariance ESPRIT-based algorithm with aperture extension using the defined matrix blocks to estimate two-dimensional directions of the signals. The MIMED can provide highly accurate and unambiguous direction estimates by extending the array element spacing beyond a half-wavelength. Finally, we present several simulation results to demonstrate the superiority of the MIMED.

Design and Simulation of a Pipeline Analog-to-Digital Converter

2012 ◽  
Vol 182-183 ◽  
pp. 1154-1158
Author(s):  
Guo Ping Chen ◽  
Xian Zhong Jian ◽  
Er Liang Xiao
Keyword(s):  
Sampling Frequency ◽  
System Model ◽  
Low Power Consumption ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Pipeline Adc ◽  
Analog To Digital ◽  
Simulation Results ◽  
Set Up ◽  
Accuracy Speed

The pipeline Analog-to-Digital Converter is highlight for its high resolution, accuracy, speed and low power consumption. In this paper, we have completed the design and simulation of a pipeline ADC with the SIMULINK toolbox of MATLAB. The model of 1.5 bit per stage was set up, and nine stages were connected to establish the system model. The system model can work correctly at 100MHz sampling frequency and reach 10 bit resolution. The simulation results can verify the correction of the pipeline ADC theory.

A 0.975 μW 10-bit 100 kS/s SAR ADC with an energy-efficient and area-efficient switching scheme

2017 ◽  
Vol 31 (19-21) ◽  
pp. 1740051 ◽  
Author(s):  
Yunfeng Hu ◽  
Chao Xiong ◽  
Bin Li
Keyword(s):  
Power Supply ◽  
Energy Efficient ◽  
Figure Of Merit ◽  
Sampling Rate ◽  
Cmos Technology ◽  
Digital Converter ◽  
Switching Scheme ◽  
Analog To Digital ◽  
Area Reduction ◽  
Area Efficient

A 10-bit successive approximation register (SAR) analog-to-digital converter (ADC) with an energy-efficient and area-efficient switching scheme was presented. By using C-2C dummy capacitor and an extra reference [Formula: see text] for the last capacitor, the proposed switching scheme achieves 97.65% switching energy saving, 87.2% capacitor area reduction and 47.06% switches reduction, compare to conventional switching scheme. The ADC was implemented in a 180 nm CMOS technology 1.8 V power supply, at sampling rate of 100 kS/s, the ADC achieves an SNDR of 57.84 dB and consumes 0.975 [Formula: see text], resulting in a figure-of-merit (FOM) of 15.3 fJ/conversion-step.

100 MS/s, 10-BIT ADC USING PIPELINED SUCCESSIVE APPROXIMATION

2014 ◽  
Vol 23 (05) ◽  
pp. 1450057
Author(s):  
SAHAR SARAFI ◽  
KHEYROLLAH HADIDI ◽  
EBRAHIM ABBASPOUR ◽  
ABU KHARI BIN AAIN ◽  
JAVAD ABBASZADEH
Keyword(s):  
Successive Approximation ◽  
Sar Adc ◽  
Cmos Process ◽  
Pipelined Adc ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Process Technology ◽  
Total Conversion ◽  
Analog To Digital ◽  
Simulation Results

This paper presents an analog-to-digital converter (ADC), using pipelined successive approximation register (SAR) architecture. The structure which is a combination of SAR-ADC and pipelined ADC benefits from each of their advantages. A new synchronization method is proposed to improve the pipelined SAR-ADC's speed. The proposed method reduces the total conversion without limiting the ADC performance. To evaluate the proposed method a 10-bit 100 MS/s is designed in 0.5 μm CMOS process technology. According to the obtained simulation results, the designed ADC digitizes a 9-MHz input with 54.19 dB SNDR while consuming 57.3 mw from a 5-V supply.

scholarly journals A 1000 Mhz Low Power and High Speed 8-Bit Flash ADC Architecture using 90nm Cmos Technology

2019 ◽  
Vol 8 (11S) ◽  
pp. 11-19
Keyword(s):  
Comparative Analysis ◽  
High Resolution ◽  
Low Power ◽  
Time Domain ◽  
High Speed ◽  
Sampling Rate ◽  
Cmos Technology ◽  
Digital Converter ◽  
Flash Adc ◽  
Analog To Digital

The design objective is to implement a Low power, High speed and High resolution Flash ADC with increased sampling rate. To make this possible the blocks of ADC are analyzed. The resistive ladder, comparator block, encoder block are the major modules of flash ADC. Firstly, the comparator block is designed so that it consumes low power. A NMOS latch based, PMOS LATCH based and a Strong ARM Latch based comparators were designed separately. A comparative analysis is made with the comparator designs. Comparators in the design is reduced to half by using time domain interpolation. Then a reference subtraction block is designed to generate the subtraction value of voltages easily and its given as input to comparator. Then a more efficient and low power consuming fat tree encoder is designed. Once all the blocks were ready, a 8 bit Flash Analog to Digital Converter was designed using 90nm CMOS technology and all the parameters such as sampling rate, power consumption, resolution were obtained and compared with other works.

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