An Advanced Traveling Wave Matching Network for DC-12GHz Variable Gain Amplifier Design

2013 ◽  
Vol 321-324 ◽  
pp. 331-335
Author(s):  
Shan Wen Hu ◽  
Tao Chen ◽  
Huai Gao ◽  
Long Xing Shi ◽  
G.P. Li
Keyword(s):  
Traveling Wave ◽  
Noise Figure ◽  
Gain Control ◽  
Wide Band ◽  
Variable Gain Amplifier ◽  
Control Voltage ◽  
Variable Gain ◽  
Input Matching ◽  
Amplifier Design ◽  
Wave Matching

A traveling wave matching (TWM) network is proposed for broadband variable gain amplifier design. The TWM network lessens input return loss and noise figure dependence on VGA’s gain, which is adjusted by biasing of the gain control circuit. A wide band (DC to 12 GHz) VGA with the novel TWM network as input matching is implemented in 2μm InGaP/GaAs HBT (fT of 29.5GHz) technology with die size of 1×2 mm2. As gain control voltage sweeps, the VGA shows a gain tuned from -15 dB to 15 dB and an average noise figure ranging from 8dB to 6.5dB, while S11 (lower than -20dB) and S22 (lower than -10dB) almost unchanged over the operation frequency band.

A WIDEBAND CMOS CASCADED VARIABLE GAIN AMPLIFIER USING UNEQUALLY DISTRIBUTED GAIN CONTROL FOR DVB-S.2 RECEIVER

2013 ◽  
Vol 22 (09) ◽  
pp. 1340008 ◽  
Author(s):  
HYEONSEOK HWANG ◽  
HOONKI KIM ◽  
CHAN-HUI JEONG ◽  
CHAN-KEUN KWON ◽  
SANGGEUN JEON ◽  
...  
Keyword(s):  
Dynamic Range ◽  
Noise Figure ◽  
Gain Control ◽  
Cmos Technology ◽  
Variable Gain Amplifier ◽  
Control Voltage ◽  
Current Generation ◽  
Fully Integrated ◽  
Variable Gain ◽  
Current Converter

A fully integrated three stage cascaded radio frequency variable gain amplifier (RFVGA) linearly controlled by exponential current generation circuit is presented. The gain control is unequally distributed in each stage for noise figure (NF) and linearity performance. The dB-linear gain control is realized using pseudo exponential current generated by CMOS current summing circuit with a voltage to current converter. The RFVGA has over 50 dB dynamic range. Gain changes from -38.5 to 16.8 dB according to control voltage that varies from 0.5 to 1.8 V. It operates at 0.95–2.15 GHz. This design is implemented in 0.18 μm CMOS technology.

A SiGe HBT Variable Gain Amplifier for Wireless Receiver System with On-Chip Filter

2012 ◽  
Vol 155-156 ◽  
pp. 167-170
Author(s):  
Wei Jia Zhang ◽  
Bo Wang
Keyword(s):  
Silicon Germanium ◽  
Gain Control ◽  
Variable Gain Amplifier ◽  
Control Voltage ◽  
Wireless Receiver ◽  
Sige Hbt ◽  
Variable Gain ◽  
Receiver System ◽  
On Chip ◽  
Gain Stage

A using SiGe HBT variable gain amplifier (VGA) with filtering for wireless receiver system is presented in this paper. The VGA consists of three stages. The first stage is the gain control stage, and the second stage is the fixed gain stage. The third is the GM-C filter. The VGA is driven by a 3.3-V power supply, and linear gain control range varying is from 26 dB to 62dB. When control voltage varies from 0 to 1.8V. The input 1-dB compression point is -4dBm at minimum gain. The VGA is fabricated in a 0.5 μm = 80GHz and =90GHz silicon germanium heterojunction transistor technology.

scholarly journals A 40 MHz 70 dB Gain Variable Gain Amplifier Design Using the gm/ID Design Method

2009 ◽  
Vol 4 (1) ◽  
pp. 7-12
Author(s):  
Fernando Paixão Cortes ◽  
Sergio Bampi
Keyword(s):  
Design Method ◽  
Gain Control ◽  
Variable Gain Amplifier ◽  
Cmos Process ◽  
Offset Cancellation ◽  
Variable Gain ◽  
Offset Voltage ◽  
Amplifier Design ◽  
Time Offset ◽  
Bond Pads

This paper addresses the design and post-fabrication measurements of a 40 MHz CMOS Variable Gain Amplifier (VGA) with a 0 to 70 dB gain control range, using the gm/ID design methodology. The VGA architecture is based on a differential pair stage with an automatic continuous-time offset cancellation circuitry, providing an input offset voltage tolerance up to 50 mV. The 3-stage VGA was designed and fabricated through MOSIS service in an IBM 0.18 μm CMOS process. The VGA dissipates 2.6 mA from a 1.8 V supply, with 34,840 μm2 circuit area, excluding bond-pads.

A NOVEL LOW-VOLTAGE CMOS VARIABLE GAIN AMPLIFIER WITH GAIN-INDEPENDENT INPUT IMPEDANCE MATCHING FOR DTV TUNING APPLICATIONS

2009 ◽  
Vol 18 (06) ◽  
pp. 1119-1136 ◽  
Author(s):  
S. M. REZAUL HASAN
Keyword(s):  
Frequency Band ◽  
Low Voltage ◽  
Noise Figure ◽  
Supply Voltage ◽  
Impedance Matching ◽  
Variable Gain Amplifier ◽  
Control Voltage ◽  
Cmos Process ◽  
Process Technology ◽  
Variable Gain

This paper presents a novel low-voltage single stage CMOS RF Variable Gain Amplifier (RFVGA) designed in 130 nm IBM CMOS process technology using current feed-back gain-independent impedance matching. The proposed RFVGA has a nearly constant gain over the 400 MHz–1 GHz frequency band. Also, it has a 70 dB gain variation (-40 dB to 30 dB) which is decibel-linear within this frequency band for a control voltage in the range of 0.41 V–0.81 V. The RFVGA demonstrates high linearity (THD ≈ -60 dB) and noise immunity (average Noise Figure ≤ 6 dB). It has an input referred third-order intercept point (IIP3) of -1.5 dBm, and an input reflection coefficient (S11) under -8 dB within the frequency band of interest. Also, it dissipates around 5 mW using a 1.2 V power supply. Further, Monte Carlo simulations incorporating process, supply voltage and temperature variations (PVT variations) as well as mismatch between devices (based on width and length of devices) indicate that the design is quite robust. The proposed RFVGA is highly suitable for mobile digital television (DTV) tuner applications.

scholarly journals An E-Band 21-dB Variable-Gain Amplifier with 0.5-V Supply in 40-nm CMOS

Electronics ◽  
2021 ◽  
Vol 10 (7) ◽  
pp. 804
Author(s):  
Gibeom Shin ◽  
Kyunghwan Kim ◽  
Kangseop Lee ◽  
Hyun-Hak Jeong ◽  
Ho-Jin Song
Keyword(s):  
Power Consumption ◽  
Frequency Band ◽  
Noise Figure ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Operating Frequency ◽  
Variable Gain Amplifier ◽  
Variable Gain ◽  
Operating Frequency Band ◽  
Shunt Capacitors

This paper presents a variable-gain amplifier (VGA) in the 68–78 GHz range. To reduce DC power consumption, the drain voltage was set to 0.5 V with competitive performance in the gain and the noise figure. High-Q shunt capacitors were employed at the gate terminal of the core transistors to move input matching points for easy matching with a compact transformer. The four stages amplifier fabricated in 40-nm bulk complementary metal oxide semiconductor (CMOS) showed a peak gain of 24.5 dB at 71.3 GHz and 3‑dB bandwidth of more than 10 GHz in 68–78 GHz range with approximately 4.8-mW power consumption per stage. Gate-bias control of the second stage in which feedback capacitances were neutralized with cross-coupled capacitors allowed us to vary the gain by around 21 dB in the operating frequency band. The noise figure was estimated to be better than 5.9 dB in the operating frequency band from the full electromagnetic (EM) simulation.

Design of 3.1-10.6GHz CMOS LNA Based on Input Matching Technique of Common-Gate Topology

2013 ◽  
Vol 479-480 ◽  
pp. 1014-1017
Author(s):  
Yi Cheng Chang ◽  
Meng Ting Hsu ◽  
Yu Chang Hsieh
Keyword(s):  
Noise Figure ◽  
Supply Voltage ◽  
Average Power ◽  
Wide Band ◽  
Low Noise ◽  
Input Matching ◽  
Common Gate ◽  
Cmos Lna ◽  
Noise Amplifier ◽  
Is Design

In this study, three stage ultra-wide-band CMOS low-noise amplifier (LNA) is presented. The UWB LNA is design in 0.18μm TSMC CMOS technique. The LNA input and output return loss are both less than-10dB, and achieved 10dB of average power gain, the minimum noise figure is 6.55dB, IIP3 is about-9.5dBm. It consumes 11mW from a 1.0-V supply voltage.

scholarly journals A 1 to 32 GHz broadband multi-octave receiver for monolithic integrated vector network analyzers in SiGe technology

2018 ◽  
Vol 10 (5-6) ◽  
pp. 717-728
Author(s):  
Marco Dietz ◽  
Andreas Bauch ◽  
Klaus Aufinger ◽  
Robert Weigel ◽  
Amelie Hagelauer
Keyword(s):  
Noise Figure ◽  
Gain Control ◽  
Wide Frequency Range ◽  
Low Noise ◽  
Vector Network Analyzer ◽  
Ultra Wideband ◽  
Network Analyzer ◽  
Active Mixer ◽  
Input Matching ◽  
Better Than

AbstractA multi-octave receiver chain is presented for the use in a monolithic integrated vector network analyzer. The receiver exhibits a very wide frequency range of 1–32 GHz, where the gain meets the 3 dB-criterion. The differential receiver consists of an ultra-wideband low noise amplifier, an active mixer and an output buffer and exhibits a maximum conversion gain (CG) of 16.6 dB. The main design goal is a very flat CG over five octaves, which eases calibration of the monolithic integrated vector network analyzer. To realize variable gain functionality, without losing much input matching, an extended gain control circuit with additional feedback branch is shown. For the maximum gain level, a matching better than −10 dB is achieved between 1–28 GHz, and up to 30.5 GHz the matching is better than −8.4 dB. For both, the input matching and the gain of the LNA, the influence of the fabrication tolerances are investigated. A second gain control is implemented to improve isolation. The measured isolations between RF-to-LO and LO-to-RF are better than 30 dB and 60 dB, respectively. The LO-to-IF isolation is better than 35 dB. The noise figure of the broadband receiver is between 4.6 and 5.8 dB for 4–32 GHz and the output referred 1-dB-compression-point varies from 0.1 to 4.3 dBm from 2–32 GHz. The receiver draws a current of max. 66 mA at 3.3 V.

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