A NOVEL LOW-VOLTAGE CMOS VARIABLE GAIN AMPLIFIER WITH GAIN-INDEPENDENT INPUT IMPEDANCE MATCHING FOR DTV TUNING APPLICATIONS

2009 ◽  
Vol 18 (06) ◽  
pp. 1119-1136 ◽  
Author(s):  
S. M. REZAUL HASAN
Keyword(s):  
Frequency Band ◽  
Low Voltage ◽  
Noise Figure ◽  
Supply Voltage ◽  
Impedance Matching ◽  
Variable Gain Amplifier ◽  
Control Voltage ◽  
Cmos Process ◽  
Process Technology ◽  
Variable Gain

This paper presents a novel low-voltage single stage CMOS RF Variable Gain Amplifier (RFVGA) designed in 130 nm IBM CMOS process technology using current feed-back gain-independent impedance matching. The proposed RFVGA has a nearly constant gain over the 400 MHz–1 GHz frequency band. Also, it has a 70 dB gain variation (-40 dB to 30 dB) which is decibel-linear within this frequency band for a control voltage in the range of 0.41 V–0.81 V. The RFVGA demonstrates high linearity (THD ≈ -60 dB) and noise immunity (average Noise Figure ≤ 6 dB). It has an input referred third-order intercept point (IIP3) of -1.5 dBm, and an input reflection coefficient (S11) under -8 dB within the frequency band of interest. Also, it dissipates around 5 mW using a 1.2 V power supply. Further, Monte Carlo simulations incorporating process, supply voltage and temperature variations (PVT variations) as well as mismatch between devices (based on width and length of devices) indicate that the design is quite robust. The proposed RFVGA is highly suitable for mobile digital television (DTV) tuner applications.

scholarly journals An E-Band 21-dB Variable-Gain Amplifier with 0.5-V Supply in 40-nm CMOS

Electronics ◽  
2021 ◽  
Vol 10 (7) ◽  
pp. 804
Author(s):  
Gibeom Shin ◽  
Kyunghwan Kim ◽  
Kangseop Lee ◽  
Hyun-Hak Jeong ◽  
Ho-Jin Song
Keyword(s):  
Power Consumption ◽  
Frequency Band ◽  
Noise Figure ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Operating Frequency ◽  
Variable Gain Amplifier ◽  
Variable Gain ◽  
Operating Frequency Band ◽  
Shunt Capacitors

This paper presents a variable-gain amplifier (VGA) in the 68–78 GHz range. To reduce DC power consumption, the drain voltage was set to 0.5 V with competitive performance in the gain and the noise figure. High-Q shunt capacitors were employed at the gate terminal of the core transistors to move input matching points for easy matching with a compact transformer. The four stages amplifier fabricated in 40-nm bulk complementary metal oxide semiconductor (CMOS) showed a peak gain of 24.5 dB at 71.3 GHz and 3‑dB bandwidth of more than 10 GHz in 68–78 GHz range with approximately 4.8-mW power consumption per stage. Gate-bias control of the second stage in which feedback capacitances were neutralized with cross-coupled capacitors allowed us to vary the gain by around 21 dB in the operating frequency band. The noise figure was estimated to be better than 5.9 dB in the operating frequency band from the full electromagnetic (EM) simulation.

Research and Analysis of Tunable Differential N-Path Band-Pass Filter

2020 ◽  
pp. 2150055
Author(s):  
Shuxiang Song ◽  
Guolun Liu ◽  
Mingcan Cen ◽  
Chaobo Cai
Keyword(s):  
Bandpass Filter ◽  
Noise Figure ◽  
Supply Voltage ◽  
Impedance Matching ◽  
Transmission Function ◽  
Center Frequency ◽  
Cmos Process ◽  
Band Pass Filter ◽  
Pass Filter ◽  
Circuit Structure

Traditional filters usually have low Q and gain values and it is difficult to adjust their center frequencies. Moreover, it is very complicated to analyze their transmission charateristics through conventional methods. Therefore, in this paper, a tunable differential N-path bandpass filter that uses a new adjoint network method to analyze the transmission characteristics of the differential N-path structure is proposed. The filter circuit adopts a novel circuit structure consisting of two differential N-path structures, two transconductance amplifiers and an off-chip transformer. The differential structure eliminates even harmonics, the transconductance amplifier increases the circuit gain and the off-chip transformer acts as a balun, improving the filter’s Q value and achieving impedance matching. Unlike the traditional switching capacitance method used for analyzing the differential circuit structure, the method proposed in this paper does not involve complicated calculus operations. In fact, the method greatly simplifies these complex operations, and the transmission function of the circuit can be obtained through simple algebraic operations. The proposed filter was designed using TSMC 180[Formula: see text]nm CMOS process. Simulation results for a differential four-path bandpass filter formed under 1.2[Formula: see text]V supply voltage show that the gain of the filter is greater than 8.5 dB, the center frequency can be adjusted from 0.1[Formula: see text]GHz to 1[Formula: see text]GHz, the in-band insertion loss S11 is greater than 10 dB, the out-of-band IIP3 is greater than 10 dBm, the out-of-band rejection is 28 dB and the noise figure is less than 2.2 dB at [Formula: see text][Formula: see text]MHz.

130 nm CMOS Bulk-Driven Variable Gain Amplifier for Low-Voltage Applications

2017 ◽  
Vol 26 (08) ◽  
pp. 1740003 ◽  
Author(s):  
Daniel Arbet ◽  
Viera Stopjaková ◽  
Martin Kováč ◽  
Lukáš Nagy ◽  
Matej Rakús ◽  
...  
Keyword(s):  
Low Voltage ◽  
Supply Voltage ◽  
Input Voltage ◽  
Cmos Technology ◽  
Variable Gain Amplifier ◽  
Voltage Range ◽  
Variable Gain ◽  
Wide Scale ◽  
Simulation Results ◽  
Low Supply Voltage

In this paper, a variable gain amplifier (VGA) designed in 130 nm CMOS technology is presented. The proposed amplifier is based on the bulk-driven (BD) design approach, which brings a possibility to operate with low supply voltage. Since the supply voltage of only 0.6 V is used for the amplifier to operate, there is no risk of latch-up event that usually represents the main drawback of the BD circuit systems. BD transistors are employed in the input differential stage, which makes it possible to operate in rail-to-rail input voltage range. Achieved simulation results indicate that gain of the proposed VGA can be varied in a wide scale, which together with the low supply voltage feature make the proposed amplifier useful for low-voltage and low-power applications. An additional circuit responsible for maintaining the linear-in-decibel gain dependency of the VGA is also addressed. The proposed circuit block avails arbitrary shaping of the curve characterizing the gain versus the controlling voltage dependency.

A 2.4 GHz Low Voltage Low Power Folded Down-Conversion Quadrature Mixer Design

2013 ◽  
Vol 760-762 ◽  
pp. 526-530
Author(s):  
Ming Li ◽  
Zhi Qun Li ◽  
Chen Jian Wu ◽  
Meng Zhang ◽  
Jia Cao ◽  
...  
Keyword(s):  
Low Voltage ◽  
Noise Figure ◽  
Supply Voltage ◽  
Cmos Process ◽  
Folded Structure ◽  
Single Side ◽  
Mixer Design ◽  
Low Supply Voltage ◽  
Single Side Band ◽  
Down Conversion

This paper introduces a 2.4 GHz down-conversion quadrature mixer which applied in the Wireless Sensor Network (WSN). The mixer uses a folded structure which is modified based on the conventional Gilbert mixer. It is designed in 0.18μm RF CMOS process with a low supply voltage of 1V. The post-simulation results show that the mixer achieves a conversion gain (CG) of 9.0dB, the input 1dB compression point (IP1dB) of-7.6dBm, the third-order input intercept point (IIP3) of 2.2dBm, and the single side-band (SSB) noise figure (NF) is 13.9dB. The mixer core consumes current about 1.2mA from a 1V power supply.

An Advanced Traveling Wave Matching Network for DC-12GHz Variable Gain Amplifier Design

2013 ◽  
Vol 321-324 ◽  
pp. 331-335
Author(s):  
Shan Wen Hu ◽  
Tao Chen ◽  
Huai Gao ◽  
Long Xing Shi ◽  
G.P. Li
Keyword(s):  
Traveling Wave ◽  
Noise Figure ◽  
Gain Control ◽  
Wide Band ◽  
Variable Gain Amplifier ◽  
Control Voltage ◽  
Variable Gain ◽  
Input Matching ◽  
Amplifier Design ◽  
Wave Matching

A traveling wave matching (TWM) network is proposed for broadband variable gain amplifier design. The TWM network lessens input return loss and noise figure dependence on VGA’s gain, which is adjusted by biasing of the gain control circuit. A wide band (DC to 12 GHz) VGA with the novel TWM network as input matching is implemented in 2μm InGaP/GaAs HBT (fT of 29.5GHz) technology with die size of 1×2 mm2. As gain control voltage sweeps, the VGA shows a gain tuned from -15 dB to 15 dB and an average noise figure ranging from 8dB to 6.5dB, while S11 (lower than -20dB) and S22 (lower than -10dB) almost unchanged over the operation frequency band.

A WIDEBAND CMOS CASCADED VARIABLE GAIN AMPLIFIER USING UNEQUALLY DISTRIBUTED GAIN CONTROL FOR DVB-S.2 RECEIVER

2013 ◽  
Vol 22 (09) ◽  
pp. 1340008 ◽  
Author(s):  
HYEONSEOK HWANG ◽  
HOONKI KIM ◽  
CHAN-HUI JEONG ◽  
CHAN-KEUN KWON ◽  
SANGGEUN JEON ◽  
...  
Keyword(s):  
Dynamic Range ◽  
Noise Figure ◽  
Gain Control ◽  
Cmos Technology ◽  
Variable Gain Amplifier ◽  
Control Voltage ◽  
Current Generation ◽  
Fully Integrated ◽  
Variable Gain ◽  
Current Converter

A fully integrated three stage cascaded radio frequency variable gain amplifier (RFVGA) linearly controlled by exponential current generation circuit is presented. The gain control is unequally distributed in each stage for noise figure (NF) and linearity performance. The dB-linear gain control is realized using pseudo exponential current generated by CMOS current summing circuit with a voltage to current converter. The RFVGA has over 50 dB dynamic range. Gain changes from -38.5 to 16.8 dB according to control voltage that varies from 0.5 to 1.8 V. It operates at 0.95–2.15 GHz. This design is implemented in 0.18 μm CMOS technology.

A LOW-VOLTAGE SCALABLE (1.8 V–0.75 V) CMOS FOLDED-CASCODE LC QUADRATURE VCO FOR RF RECEIVERS

2010 ◽  
Vol 19 (04) ◽  
pp. 835-857 ◽  
Author(s):  
S. M. REZAUL HASAN
Keyword(s):  
Monte Carlo ◽  
Phase Noise ◽  
Low Voltage ◽  
Supply Voltage ◽  
Voltage Scaling ◽  
Center Frequency ◽  
Cmos Process ◽  
Process Technology ◽  
Folded Cascode ◽  
Supply Voltage Scaling

This paper presents a scalable low voltage CMOS folded-cascode quadrature voltage controlled oscillator (QVCO) design for radio-frequency (RF) applications using the TSMC 0.18 μm 6M1P CMOS process technology. The simulated startup behavior of this proposed QVCO topology indicates that, the QVCO is free from bi-modal oscillation (frequency ambiguity). The QVCO provided extended voltage swing with the supply voltage scalable in the range of 1.8 V to 0.75 V. The QVCO operates in the frequency range of 4 GHz to 3 GHz (corresponding to supply voltage scaling in the range of 1.8 V to 0.75 V) with around 11.7% tuning range and low quadrature error. The QVCO had a power consumption under 10 mW within the specified supply voltage scaling range. Phase noise simulations using the Monte Carlo analysis provide an approximate phase noise estimate of ≈ -150 dBc/Hz at an offset of 600 KHz from the center frequency (@3.7 GHz) for operation using the 1.8 V supply voltage, using moderate inductor-Q values. Monte Carlo simulations were also carried out to determine the effects of the process, voltage and temperature variations.

A Fully Differential Variable Gain Amplifier for Portable Impedance Sensing Applications

2019 ◽  
Vol 7 ◽  
Author(s):  
Jorge Pérez Bailón ◽  
Jaime Ramírez-Angulo ◽  
Belén Calvo ◽  
Nicolás Medrano
Keyword(s):  
Power Consumption ◽  
Active Area ◽  
Variable Gain Amplifier ◽  
Cmos Process ◽  
Current Steering ◽  
Impedance Sensing ◽  
Variable Gain ◽  
Fully Differential ◽  
Sensing Applications ◽  
Constant Bandwidth

This paper presents a Variable Gain Amplifier (VGA) designed in a 0.18 μm CMOS process to operate in an impedance sensing interface. Based on a transconductance-transimpedance (TC-TI) approach with intermediate analog-controlled current steering, it exhibits a gain ranging from 5 dB to 38 dB with a constant bandwidth around 318 kHz, a power consumption of 15.5 μW at a 1.8 V supply and an active area of 0.021 mm2.

Analysis of 6T SRAM Cell in Different Technologies

2017 ◽  
Vol MCSP2017 (01) ◽  
pp. 7-10 ◽  
Author(s):  
Subhashree Rath ◽  
Siba Kumar Panda
Keyword(s):  
Low Power ◽  
Data Storage ◽  
Low Voltage ◽  
Random Access ◽  
Storage Device ◽  
Cmos Process ◽  
Process Technology ◽  
Digital Devices ◽  
Noise Margin ◽  
Sram Cell

Static random access memory (SRAM) is an important component of embedded cache memory of handheld digital devices. SRAM has become major data storage device due to its large storage density and less time to access. Exponential growth of low power digital devices has raised the demand of low voltage low power SRAM. This paper presents design and implementation of 6T SRAM cell in 180 nm, 90 nm and 45 nm standard CMOS process technology. The simulation has been done in Cadence Virtuoso environment. The performance analysis of SRAM cell has been evaluated in terms of delay, power and static noise margin (SNM).

scholarly journals RF Transceiver for the Multi-Mode Radar Applications

Sensors ◽  
2021 ◽  
Vol 21 (5) ◽  
pp. 1563
Author(s):  
Jae Kwon Ha ◽  
Chang Kyun Noh ◽  
Jin Seop Lee ◽  
Ho Jin Kang ◽  
Yu Min Kim ◽  
...  
Keyword(s):  
Long Range ◽  
Integrated Circuit ◽  
Flicker Noise ◽  
Noise Figure ◽  
Supply Voltage ◽  
Doppler Frequency ◽  
Cmos Process ◽  
Rf Transceiver ◽  
Dc Offset ◽  
Multi Mode

In this work, a multi-mode radar transceiver supporting pulse, FMCW and CW modes was designed as an integrated circuit. The radars mainly detect the targets move by using the Doppler frequency which is significantly affected by flicker noise of the receiver from several Hz to several kHz. Due to this flicker noise, the long-range detection performance of the radars is greatly reduced, and the accuracy of range to the target and velocity is also deteriorated. Therefore, we propose a transmitter that suppresses LO leakage in consideration of long-range detection, target distance, velocity, and noise figure. We also propose a receiver structure that suppresses DC offset due to image signal and LO leakage. The design was conducted with TSMC 65 nm CMOS process, and the designed and fabricated circuit consumes a current of 265 mA at 1.2 V supply voltage. The proposed transmitter confirms the LO leakage suppression of 37 dB at 24 GHz. The proposed receiver improves the noise figure by about 20 dB at 100 Hz by applying a double conversion architecture and an image rejection, and it illustrates a DC rejection of 30 dB. Afterwards, the operation of the pulse, FMCW, and CW modes of the designed radar in integrated circuit was confirmed through experiment using a test PCB.

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