Compensation Design of CIC Decimation Filter for Seismic Prospecting

In seismic prospecting, the over sample combined with low quantity is used to converter input analog signals to 1-bit data flow. In order to realize decimation filtering for the high speed low resolution signal produced in the process of seismic prospecting, the CIC decimation filter is introduced into seismic survey system to achieve decimation and filting. The principle and the shortcoming were analyzed; finally an ISOP filter is introduced to compensate the pass-band attenuation, Simulation showed it could improve the performance of CIC filter, the cascade of CIC and ISOP is suitable for seismic prospecting system.

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FPGA Based Performance Analysis of Multistage CIC Decimation Filter Design with former CIC Filter for WiMAX Applications

International Journal of Engineering and Advanced Technology - Regular Issue ◽

10.35940/ijeat.f9556.088619 ◽

2019 ◽

Vol 8 (6) ◽

pp. 5084-5089

Keyword(s):

Frequency Response ◽

Filter Design ◽

Stop Band ◽

Pass Band ◽

Two Stage ◽

Simulink Model ◽

Cic Filter ◽

Decimation Filter ◽

Two Stages ◽

Kaiser Window

The motto of this paper is to design and realize decimation filter using CIC filter. The main drawback of this filter is there is large droop in pass band and very less attenuation in stop band. So, to improve the frequency response of CIC filter we go for two stage realization of CIC filter. At the initial stage we use CIC filter and in the last stage we use Kaiser Window and improve the characteristics of filter design. When we design a filter using multistage methodology the order of the filter as well as power also decreases. Tools used are MATLAB Simulink Model and Xilinx system generator and realization is done on Virtex V-XC5VLX110T-3ff136. In this paper the proposed two stage realization is compared with respect to two stages Kaiser window realization in the terms of number of LUT’s required, slices as well as power dissipation and improvements in frequency response with respect to conventional CIC filter are compared

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Design and Research of Digital Decimation Filter Based on FPGA

Applied Mechanics and Materials ◽

10.4028/www.scientific.net/amm.105-107.2086 ◽

2011 ◽

Vol 105-107 ◽

pp. 2086-2091

Author(s):

Yao Li

Keyword(s):

High Speed ◽

Sampling Rate ◽

Comb Filter ◽

Pass Filter ◽

Low Pass Filter ◽

Low Pass ◽

Cic Filter ◽

Decimation Filter ◽

Fpga Chip ◽

Digital Down Conversion

This paper studies and analyses various digital filter and decimation structure. On this basis, by using QUARTUS development system design the decimation device modules, through the waveform simulation validated its correctness. Finally,a program is written into FPGA chip by the hardware platform. In the digital down conversion (DDC), CIC (cascade integral comb) filter plays an important role. It is mainly used for sampling rate, as well as low-pass filter effect. The main characteristics of CIC filter, using only adders, subtractor and register (no multiplier), so fewer resources occupied, implementation is simple and high speed. Based on the analysis of the principle of CIC filter,simulate and synthesize based on the theory of using VHDL language in FPGA. And successful application in the development of DDC chip. Keyword: CIC (cascade integral comb) filter,FPGA,VHDL

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Design of a Digital Decimation Filter for High-Precision 4-Order Sigma-Delta ADC

Key Engineering Materials ◽

10.4028/www.scientific.net/kem.503.415 ◽

2012 ◽

Vol 503 ◽

pp. 415-419 ◽

Cited By ~ 2

Author(s):

Wei Ping Chen ◽

Qiang Fu ◽

Xiao Wei Liu ◽

Yan Xiao ◽

Bin Zhang ◽

...

Keyword(s):

High Precision ◽

Sampling Rate ◽

Stop Band ◽

Cutoff Frequency ◽

Pass Band ◽

Sigma Delta ◽

Band Filter ◽

Cic Filter ◽

Decimation Filter ◽

Sigma Delta Adc

In this paper, a design of a digital decimation filter which has a output of 24 bits for high-precision 4-ordes Σ-Δ ADC is proposed. The digital decimation filter includes a CIC filter, a compensation filter and a half band filter. The over-sampling rate of the digital decimation filter is 256, the cutoff frequency is 1kHz, the coefficient of the pass-band ripple is -0.25dB, the stop-band attenuation is -162dB, simulation results using Matlab and modelsim are correct, the result of the FPGA verification shows that the design meet the requirement of the high-precision 4-ordes Σ-Δ ADC.

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Control of a lamination process

Proceedings of the Institution of Mechanical Engineers Part E Journal of Process Mechanical Engineering ◽

10.1243/095440805x7008 ◽

2005 ◽

Vol 219 (1) ◽

pp. 69-81 ◽

Cited By ~ 1

Author(s):

R Whalley ◽

M Ebrahimi

Keyword(s):

High Speed ◽

Closed Loop ◽

Cost Effective ◽

Closed Loop System ◽

Design Validation ◽

Control Effort ◽

Speed Of Response ◽

Feedback Compensation ◽

Lamination Process ◽

Compensation Design

A high-speed laminating machine for a fabric coating and conversion process is considered. Following analysis procedures, state-space and the admittance transfer function descriptions for the system are derived. Regulation of the fabric tension owing to heat shrinkage and environmental and coating variations is necessary. An optimum, minimum control effort strategy is proposed, enabling simple cost effective regulation, without the use of active elements. The speed of response of the system is improved by the use of feedback compensation. Design validation, via simulation, obtaining the open- and closed-loop system responses is employed, demonstrating the achievement of smooth, almost monotonic variations in tension following reference changes, as specified.

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A Sigma-Delta ADC for Signal Conditioning IC of Automotive Piezo-Resistive Pressure Sensors with over 80 dB SNR

Sensors ◽

10.3390/s18124199 ◽

2018 ◽

Vol 18 (12) ◽

pp. 4199 ◽

Cited By ~ 1

Author(s):

Behnam Samadpoor Rikan ◽

Sang-Yun Kim ◽

Nabeel Ahmad ◽

Hamed Abbasizadeh ◽

Muhammad Riaz Ur Rehman ◽

...

Keyword(s):

Input Signal ◽

Flicker Noise ◽

Signal To Noise Ratio ◽

Pressure Sensors ◽

High Gain ◽

Cmos Process ◽

Signal Conditioning ◽

Sigma Delta ◽

Cic Filter ◽

Decimation Filter

This paper presents a second-order discrete-time Sigma-Delta (SD) Analog-to-Digital Converter (ADC) with over 80 dB Signal to Noise Ratio (SNR), which is applied in a signal conditioning IC for automotive piezo-resistive pressure sensors. To reduce the flicker noise of the structure, choppers are used in every stage of the high gain amplifiers. Besides, to reduce the required area and power, only the CIC filter structure is adopted as a decimation filter. This filter has a configurable structure that can be applied to different data rates and input signal bandwidths. The proposed ADC was fabricated and measured in a 0.18-µm CMOS process. Due to the application of only a CIC filter, the total active area of the SD-ADC and reference generator is 0.49 mm2 where the area of the decimation filter is only 0.075 mm2. For the input signal bandwidth of 1.22 kHz, it achieved over 80 dB SNR in a 2.5 MHz sampling frequency while consuming 646 µW power.

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Design of Equivalent Device Based on Ethernet Communication

Advanced Materials Research ◽

10.4028/www.scientific.net/amr.341-342.868 ◽

2011 ◽

Vol 341-342 ◽

pp. 868-872

Author(s):

Hui Xin Zhang ◽

Yan Lu Zheng ◽

Yan Ran Chen ◽

Hai Guang Yang

Keyword(s):

Measurement System ◽

High Speed ◽

Data Transfer ◽

Long Distance ◽

Aircraft Measurement ◽

Transfer Mode ◽

Analog Signals ◽

Self Testing ◽

Test Platform ◽

Equivalent Test

To match, test, and determine the working conditions and correctness of each function of the aircraft measurement system. This article proposes a design of equivalent test platform which can produce digital and analog signals for the self-testing of measurement system. By using the ethernet protocol chip W5300 to achieve the high-speed communication between host computer and equivalent device. Communication uses UDP unicast data transfer mode with advantages of high-speed and long-distance transmission, and the Phenomenon of data packet loss is not easy in transmission.

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High-Speed Superconductive Decimation Filter for Sigma-Delta Analog to Digital Converter

Journal of Physics Conference Series ◽

10.1088/1742-6596/871/1/012068 ◽

2017 ◽

Vol 871 ◽

pp. 012068

Author(s):

Tomu Wakamatsu ◽

Yuki Yamanashi ◽

Nobuyuki Yoshikawa

Keyword(s):

High Speed ◽

Analog To Digital Converter ◽

Digital Converter ◽

Sigma Delta ◽

Analog To Digital ◽

Decimation Filter

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Methods for Simultaneous Improvement of Comb Pass Band and Folding Bands

Encyclopedia of Information Science and Technology, Fourth Edition ◽

10.4018/978-1-5225-2255-3.ch536 ◽

2018 ◽

pp. 6171-6183

Author(s):

Gordana Jovanovic Dolecek

Keyword(s):

Design Methods ◽

Comb Filter ◽

Signal Spectrum ◽

Pass Band ◽

Original Spectrum ◽

Compensator Design ◽

Decimation Filter

This decimation introduces the replicas of the main signal spectrum. If the signal is not properly filtered, the overlapping of the repeated replicas of the original spectrum, called aliasing, may occur. The aliasing may destroy the useful information of the decimated signal and must be eliminated by the filter which precedes the decimation, called decimation filter. The most popular decimation filter is a comb filter, usually used in the first stage of decimation. However its magnitude characteristic is not flat in the pass band of interest and there is not enough attenuation in the folding bands. Different methods are proposed to improve comb magnitude characteristic. This article presents an overview of methods for simultaneous improvement of comb magnitude characteristic in both: pass band and folding bands. The methods are divided into three main groups: Sharpening-based methods, Corrector–based methods, and Methods based on the combination of alias rejection and compensator design methods.

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