Design of the Approved Low Power Energy Recovery Logic Circuit

2013 ◽  
Vol 662 ◽  
pp. 851-855
Author(s):  
Jian Ying Shi ◽  
Hui Ya Li ◽  
Yan Bin Xu
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Energy Recovery ◽  
Logic Circuits ◽  
Logic Circuit ◽  
Lower Power ◽  
Transmission Gate ◽  
Bootstrap Technique

An approved energy recovery logic circuit (AERL) was designed in this paper. In order to further reduce the power consumption of energy recovery logic circuits, the NMOS transmission gate and NMOS bootstrap technique ware used. The characteristics of the AERL circuit ware simulated using 0.5 micrometer BSIM3V3 spice models in HSPICE. The results show that the AERL circuit has much lower power consumption compared with PT-BCRL, BERL, ECRL and 2N2N-2P logic.

Design of Digital Operational Units with Low Power Consumption

2021 ◽  
Vol 12 (2) ◽  
pp. 63-73
Author(s):  
N. A. Avdeev ◽  
◽  
P. N. Bibilo ◽  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Logic Circuits ◽  
Logic Circuit ◽  
Digital Design ◽  
Low Power Consumption ◽  
Structural Description ◽  
Clock Gating ◽  
Vhdl Code

The lowering of power consumption in CMOS VLSI digital systems is one of the most important problems that appear now for developers of CAD systems. One of the effective approaches to lowering the dynamic power consumption is creation of an algorithmic description of the VHDL project, which provides for the deactivation of some functional blocks which are not necessary in particular moments. Contemporary synthesizers fulfill the high level synthesis of logic circuits by substitution of description of each VHDL construction with functionally structural description of a proper logic subcircuit. The results of digital logic circuit synthesis (the number of logic elements and power consumption) depend significantly on initial VHDL code. During initial VHDL code development it is possible to use different approaches to improve some parameters of synthesized logic circuit. At the algorithmic level of the digital design, it is necessary to provide for disconnection of the units, which cause the higher power consumption. In this paper such methods of algorithmic VHDL description of logic circuit are studied. The efficiency of the proposed methods is compared with the traditional method of VHDL-description which does not take the aspect of power con­sumption into account and is oriented only to the correct functionality of the developed logic circuit. To estimate the power consumption of logic circuits the approach is used which allows applying high-speed logical VHDL-simulation of structural descriptions (netlists) of logic circuits instead of slow SPICE simulation. The main conclusion of the provided study is the following: the clock gating and the storage of operand values for complex operations as well as zero value setting for simple ones are effective methods for the VHDL description of operational units with low power consumption implemented in the CMOS basis.

A LOW-POWER AND HIGH-SPEED D FLIP-FLOP USING A SINGLE LATCH

2002 ◽  
Vol 11 (01) ◽  
pp. 51-55
Author(s):  
ROBERT C. CHANG ◽  
L.-C. HSU ◽  
M.-C. SUN
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
Operating Frequency ◽  
Flip Flop ◽  
Lower Power ◽  
Simulation Results ◽  
Hspice Simulation

A novel low-power and high-speed D flip-flop is presented in this letter. The flip-flop consists of a single low-power latch, which is controlled by a positive narrow pulse. Hence, fewer transistors are used and lower power consumption is achieved. HSPICE simulation results show that power dissipation of the proposed D flip-flop has been reduced up to 76%. The operating frequency of the flip-flop is also greatly increased.

A Low-Power and Area-Efficient 64-Bit Digital Comparator

2016 ◽  
Vol 25 (12) ◽  
pp. 1650148 ◽  
Author(s):  
N. V. Vijaya Krishna Boppana ◽  
Saiyu Ren
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Resource Sharing ◽  
Portable Devices ◽  
Worst Case ◽  
Lower Power ◽  
Digital Comparator ◽  
Area Efficient

A new low-power and area-efficient radix-4 tree-based 64-bit digital comparator is presented in this paper. The proposed design with 64 XOR-XNOR (XE) blocks is custom implemented in 90[Formula: see text]nm 1.2[Formula: see text]V multi-threshold technology using Cadence-Virtuoso layout editor. The 64 bit comparator has an area of 1009[Formula: see text][Formula: see text], a worst case delay of 858[Formula: see text]ps, and a power consumption of 898[Formula: see text]uW at 1[Formula: see text]G bit/s. The two features, lower power consumption and smaller area compared to other published comparators, make the proposed design most suitable for low-power portable devices. Resource sharing is an important feature for the proposed design. The 64 XE blocks occupy approximately 60% (600[Formula: see text][Formula: see text]) of the total comparator area and contributes 54% (484[Formula: see text][Formula: see text]W) of the total worst power consumption. The 64 XE blocks can also be used to design XE based 64-bit adders, encryption devices, etc.

scholarly journals Various Nano-Scale Technologies: Lower Hardware Complexity of Alu Realizing Utilizing FS-GDI Approach IN 45nm AND 130nm

2021 ◽  
Vol 14 (1) ◽  
pp. 9-34
Author(s):  
Mohsen A. M. El-Bendary ◽  
◽  
M. Ayman ◽  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Delay Time ◽  
Digital Circuits ◽  
Logic Gates ◽  
Propagation Delay ◽  
Hardware Complexity ◽  
Simulation Experiments ◽  
Lower Power ◽  
Full Swing

Full Swing Gate Diffusion Input (FS-GDI) approach is power effective approach for realizing the different logic gates. In this research, this approach is utilized for realizing different four ALU design using 45nm and 130nm technologies. Also, the different low power VLSI logic styles and related past works are discussed with considering the 45nm and 65nm technologies for implementing various circuits for studying the technology size impact. The performance of the proposed ALU design is evaluated through power consumption, propagation delay and number of transistors. The variation of the ALU performance due to the used 45nm and 130nm technologies has been studied. The simulation is carried out utilizing Cadence Virtuoso simulator. The simulation experiments revealed the energy of the 4-bit ALU reduced by 32% compared to CMOS-based design and area of the digital circuits reducing. Regarding the different nano technologies, 45nm technology provides lower power consumption and delay time deceasing compared to ALU unit by 130nm technology. The presented approach of low hardware complexity achieves simplicity of the required ALU hardware through reducing the number of transistors.

Low Power Structural Design of 2–4 and 4–16 Line Decoder Logic Circuit

2020 ◽  
Vol 17 (5) ◽  
pp. 2266-2272
Author(s):  
Nikita Kar Chowdhury ◽  
R. Dhanabal ◽  
V. N. Ramakrishnan
Keyword(s):  
Low Power ◽  
Structural Design ◽  
Logic Circuit ◽  
Digital Logic ◽  
Transmission Gate

An analysis of low power 2–4 decoder and 4–16 decoders are made and comparing it with the proposed decoders. The decoder logic circuit have been made utilizing Dual Value Logic (DVL) and Transmission gate logic to actualize a fourteen transistors 2–4 decoder for limiting the transistor count. By utilizing 2–4 pre-decoders and post-decoders to execute 4–16 decoder. Blended digital logic is additionally utilized for this reason. In correlation we have execute a solitary 2–4 decoder with least transistor check and low power utilization which is utilized to structure a 4–16 decoder. CADENCE Virtuoso simulation at 90 nm technology is used and calculated the power and area. We thus made a tabular comparison of our results with the results from previous researches.

scholarly journals Design of Area Efficient, Low-Power and Reliable Transmission Gate-based 10T SRAM Cell for Biomedical Application

2021 ◽  
Author(s):  
Aswini Valluri ◽  
◽  
Sarada Musala ◽  
Muralidharan Jayabalan ◽  
◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Biomedical Application ◽  
Cmos Technology ◽  
Total Power ◽  
Silicon Area ◽  
Transmission Gate ◽  
Read Operation ◽  
Sram Cell ◽  
Total Power Consumption

There is an immense necessity of several kilo bytes of embedded memory for Biomedical systems which typically operate in the sub-threshold domain with perfect efficiency. SRAMs (Static Random Access Memory) dominates the total power consumption and the overall silicon area, as 70% of the die has been occupied by them. This brief proposes the design of a Transmission gate-based SRAM cell for Bio medical application eliminating the use of peripheral circuitry during the read operation. It commences the read operation directly with the help of Transmission gates with which the data stored in the storage nodes can be read, instead of using the precharge and sense amplifier circuits which suits better for the implantable devices. This topology offers smaller area, reduced delay, low power consumption as well as improved data stabilization in the read operation. The cell is implemented in 45nm CMOS technology operated at 0.45V.

scholarly journals Low Power Design of 2–4 and 4–16 Line Decoders

2019 ◽  
Vol 8 (9) ◽  
pp. 1220-1224
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Low Power Design ◽  
Low Power Consumption ◽  
Transmission Gate ◽  
Novel Design

Here, we are proposing a novel design of 2:4 decoder and 4:16 decoders which are designed by using line decoder concept. By using proposed design, the area and power consumption of 2:4 decoder and 4:16 decoder can be reduced. In the existing work they have used DVL (Dual Value Logic) and Transmission gate Logic to implement a 14-Transistor 2:4 decoder for minimizing the transistor count. By using 2:4 pre-decoders and post-decoders they implemented 4:16 decoders. Mixed logic is also used for this purpose. Here we have implemented a single 2:4 decoder with minimum transistor count and low power consumption which is used to design a 4:16 decoder. We implement the proposed design in Cadence Virtuoso simulation at 90nm technology and calculated the power and area.

scholarly journals AREA AND POWER OPTIMIZED D-FLIP FLOP AND SUBTRACTOR

2021 ◽  
Vol 9 (1) ◽  
pp. 159-163
Author(s):  
T. Subhashini, M. Kamaraju, K. Babulu
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Vlsi Design ◽  
Logic Circuits ◽  
Modern Technology ◽  
Power Reduction ◽  
Flip Flop ◽  
Xor Gate ◽  
Long Run

Low power is essential in today’s technology. It is most significant with high speed, small size and stability. So, power reduction is most important in modern technology using VLSI design techniques. Today most of the market necessities require low power, long run time and market which also deserve small size and high speed. In this paper several logic circuits DFF with 5 transistors and sub tractor circuit using powerless XOR gate and Groundless XNOR gates are implemented. In the proposed DFF, the area can be decreased by 62% & substarctor circuit, area decreased by 80% and power consumption of DFF and subtractor circuit are 15.4µW and 13.76µW respectively, but these are very less as compared to existing techniques.  

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