Optimization of Power and Gain in Two-Stage Op-Amp by Using Taguchis Approach

2013 ◽  
Vol 712-715 ◽  
pp. 1820-1825 ◽  
Author(s):  
Siti Amaniah Mohd Chachuli ◽  
Faiz Arith ◽  
Mohammad Idzdihar Idris
Keyword(s):  
Taguchi Method ◽  
Power Dissipation ◽  
Statistical Approach ◽  
Circuit Simulation ◽  
Power Reduction ◽  
Total Power ◽  
Two Stage ◽  
Op Amp

This paper presents a method based on statistical approach which known as Taguchi method. This method is used to optimize power dissipations and gain in a two-stage op-amp. Standard L27 which uses three factors and two outputs is chosen to optimize power and gain in the circuit. Simulation of the circuit has been implemented by using Mentor Graphics DA-IC. From the simulation, the results showed that total power dissipation has decreased from 3.9643 mW to 1.0345 mW. The percentage of power reduction is 73.9%. The overall gain also has been improved from 22 dB to 45.49 dB. The percentage of increment gain in two-stage op-amp is 56%.

Evolutionary Computation Based Sizing Technique of Nulling Resistor Compensation Based CMOS Two-Stage Op-Amp Circuit

2017 ◽  
Vol 26 (04) ◽  
pp. 1740021 ◽  
Author(s):  
Bishnu Prasad De ◽  
Kanchan Baran Maji ◽  
Rajib Kar ◽  
Durbadal Mandal ◽  
Sakti Prasad Ghoshal
Keyword(s):  
Genetic Algorithm ◽  
Evolutionary Computation ◽  
Power Dissipation ◽  
Premature Convergence ◽  
Mos Transistors ◽  
Two Stage ◽  
Design Constraints ◽  
Op Amp ◽  
Simulation Results

This article explores the comparative optimizing efficiency between two PSO variants, namely, Craziness based PSO (CRPSO) and PSO with an Aging Leader and Challengers (ALC-PSO) for the design of nulling resistor compensation based CMOS two-stage op-amp circuit. The concept of PSO is simple and it replicates the nature of bird flocking. As compared with Genetic algorithm (GA), PSO deals with less mathematical operators. Premature convergence and stagnation problem are the two major limitations of PSO technique. CRPSO and ALC-PSO techniques individually have eliminated the disadvantages of the PSO technique. In this article, CRPSO and ALC-PSO are individually employed to optimize the sizes of the MOS transistors to reduce the overall area taken by the circuit while satisfying the design constraints. The results obtained individually from CRPSO and ALC-PSO techniques are validated in SPICE environment. SPICE based simulation results justify that ALC-PSO is much better technique than CRPSO and other formerly reported methods for the design of the afore mentioned circuit in terms of the MOS area, gain and power dissipation etc.

Design Methodology for Multipliers with Active Leakage and Dynamic Power Reduction

2012 ◽  
Vol 182-183 ◽  
pp. 1440-1445
Author(s):  
Xi Tian ◽  
Fei Qiao ◽  
Zai Wang Dong ◽  
Yu Jun Liu ◽  
Yu Ting Zhao
Keyword(s):  
Input Signal ◽  
Power Dissipation ◽  
Design Methodology ◽  
Dynamic Range ◽  
Power Reduction ◽  
Total Power ◽  
Power Gating ◽  
Dynamic Power ◽  
On Chip ◽  
Novel Design

A novel design methodology for multipliers to reducing both active leakage and dynamic power using dynamic power gating is presented, where sleep transistors are inserted between the real and virtual ground rails of various parts of the multiplier which could be selectively turned on/off. On-chip sleep signals are generated from one input signal of the multiplier which has larger dynamic range. By detecting the magnitude of the input signal, the idle parts of the multiplier are identified and the power gating schemes are dynamically applied even when the multiplier is performing useful computation. Simulations show that the total power dissipation of the proposed multiplier could be reduced up to 39.3% in a typical DSP application.

scholarly journals Power Optimization of Delay Constrained Circuits

VLSI Design ◽  
2001 ◽  
Vol 12 (2) ◽  
pp. 125-138
Author(s):  
Anshuman Nayak ◽  
Malay Haldar ◽  
Prith Banerjee ◽  
Chunhong Chen ◽  
Majid Sarrafzadeh
Keyword(s):  
Power Dissipation ◽  
Short Circuit ◽  
Average Power ◽  
Accurate Estimate ◽  
Voltage Scaling ◽  
Power Reduction ◽  
Total Power ◽  
Gate Sizing ◽  
Dynamic Power ◽  
Circuit Power

We present a framework for combining Voltage Scaling (VS) and Gate Sizing (GS) techniques for power optimizations. We introduce a fast heuristic for choosing gates for sizing and voltage scaling such that the total power is minimized under delay constraints. We also use a more accurate estimate for determining the power dissipation of the circuit by taking into account the short circuit power along with the dynamic power. A better model of the short circuit power is used which takes into account the load capacitance of the gates. Our results show that the combination of VS and GS perform better than the techniques applied in isolation. An average power reduction of 73% is obtained when decisions are taken assuming dynamic power only. In contrast, average power reduction is 77% when decisons include the short circuit power dissipation.

Implementation of an Ultra Low Power Process-Insensitive Two Stage Complementary Metal Oxide Semiconductor Operational Amplifier with Enhanced Direct Current Gain at 45 nm Technology Node

2020 ◽  
Vol 18 (10) ◽  
pp. 770-775
Author(s):  
Pragati Gupta ◽  
Shyam Akashe
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Performance Metrics ◽  
Current Gain ◽  
Phase Margin ◽  
Two Stage ◽  
Gain Bandwidth ◽  
Ultra Low Power ◽  
Op Amp ◽  
Dc Gain

This paper presents an ultra low power process-insensitive two stage CMOS OP-AMP employing bulk-biasing technique realised in a standard 45 nm CMOS technology. Bulk-Biasing technique has been employed to augment the DC gain of two stage CMOS OP-AMP without having any impact on its power dissipation and output swing. In this work, high gain-bandwidth product (GBW) with appropriate phase margin is achieved through pseudo-cascode compensation approach which overcomes the drawbacks of Miller compensation technique also. Furthermore, the effect of width scaling on performance metrics of proposed OP-AMP has been analysed. The designed OP-AMP exhibits enhanced DC gain of 94.2 dB, gain-bandwidth product (GBW) of 460 MHz and adequate phase margin of 80°; with fast settling response. Also, the proposed OP-AMP has power dissipation of 27 μW and leakage current of 6.4 pA only. The design and optimisation of proposed OP-AMP is carried out at a power supply of 0.7 V under room temperature in Cadence Virtuoso tool.

scholarly journals TMaR: a two-stage MapReduce scheduler for heterogeneous environments

2020 ◽  
Vol 10 (1) ◽  
Author(s):  
Neda Maleki ◽  
Hamid Reza Faragardi ◽  
Amir Masoud Rahmani ◽  
Mauro Conti ◽  
Jay Lofstead
Keyword(s):  
Task Scheduling ◽  
Network Traffic ◽  
Input Data ◽  
Power Reduction ◽  
Heterogeneous Environments ◽  
Two Stage ◽  
Finish Time ◽  
Remote Storage ◽  
Simulation Results

Abstract In the context of MapReduce task scheduling, many algorithms mainly focus on the scheduling of Reduce tasks with the assumption that scheduling of Map tasks is already done. However, in the cloud deployments of MapReduce, the input data is located on remote storage which indicates the importance of the scheduling of Map tasks as well. In this paper, we propose a two-stage Map and Reduce task scheduler for heterogeneous environments, called TMaR. TMaR schedules Map and Reduce tasks on the servers that minimize the task finish time in each stage, respectively. We employ a dynamic partition binder for Reduce tasks in the Reduce stage to lighten the shuffling traffic. Indeed, TMaR minimizes the makespan of a batch of tasks in heterogeneous environments while considering the network traffic. The simulation results demonstrate that TMaR outperforms Hadoop-stock and Hadoop-A in terms of makespan and network traffic and achieves by an average of 29%, 36%, and 14% performance using Wordcount, Sort, and Grep benchmarks. Besides, the power reduction of TMaR is up to 12%.

scholarly journals A 0.6-V to 1-V Audio ΔΣ Modulator in 65 nm CMOS with 90.2 dB SNDR at 0.6-V

VLSI Design ◽  
2013 ◽  
Vol 2013 ◽  
pp. 1-9 ◽  
Author(s):  
Liyuan Liu ◽  
Dongmei Li ◽  
Zhihua Wang
Keyword(s):  
Power Dissipation ◽  
Total Power ◽  
Third Order ◽  
Power Cost ◽  
Threshold Voltages ◽  
Nonlinear Amplifier ◽  
Amplifier Gain ◽  
Low Threshold ◽  
Single Comparator ◽  
Circuit Techniques

This paper presents a discrete time, single loop, third order ΔΣ modulator. The input feed forward technique combined with 5-bit quantizer is adopted to suppress swings of integrators. Harmonic distortions as well as the noise mixture due to the nonlinear amplifier gain are prevented. The design of amplifiers is hence relaxed. To reduce the area and power cost of the 5-bit quantizer, the successive approximation quantizer with only a single comparator instead of traditional flash quantizer is employed. Fabricated in 65 nm CMOS, the modulator achieves 95 dB peak SNDR at 1-V supply with 24 kHz. Thanks to low swing circuit techniques and low threshold voltages of devices, the peak SNDR maintains 90.2 dB under 0.6-V low supply. The total power dissipation is 371 μW at 1-V and drops to only 133 μW at 0.6-V.

A New Optimization Strategy for Chemical Mechanical Polishing Process

2000 ◽  
Author(s):  
Gou-Jen Wang ◽  
Jau-Liang Chen ◽  
Ju-Yi Hwang
Keyword(s):  
Neural Network ◽  
Taguchi Method ◽  
Signal To Noise Ratio ◽  
Global Optimum ◽  
Optimum Process ◽  
Local Optimum ◽  
Optimization Strategy ◽  
Two Stage ◽  
Chemical Mechanical Polishing Process ◽  
Trained Neural Network

Abstract In this paper, a systematic approach to achieve global optimum CMP process is carried out. In this new approach, orthogonal array technique adopted from the Taguchi method is used for efficient experiment design. The neural network (NN) technique is then applied to model the complex CMP process. Signal to Noise Ratio (S/N) Analysis (ANOVA) technique used in the conventional Taguchi method is also implemented to obtain the local optimum process parameters. Successively, the global optimum parameters are acquired in terms of the trained neural network. In order to increase the CMP throughput, a two-stage optimal strategy is also proposed. Experimental results demonstrate that the two-stage strategy can perform better then the original approach even though the polishing time is reduced by 1/6.

A High-Speed Fully Differential Telescopic Op-Amp for Active Filter Designs in V2X Applications

2021 ◽  
Author(s):  
Furkan Barin ◽  
Ertan Zencir
Keyword(s):  
High Speed ◽  
Low Voltage ◽  
Supply Voltage ◽  
Active Filter ◽  
Ultra Wideband ◽  
Two Stage ◽  
Fully Differential ◽  
Op Amp ◽  
Current Mirrors ◽  
Design Techniques

In this paper, an ultra-wideband fully differential two-stage telescopic 65-nm CMOS op-amp is presented, which uses low-voltage design techniques such as level shifter circuits and low-voltage cascode current mirrors. The designed op-amp consists of two stages. While the telescopic first stage provides high speed and low swing, the second stage provides high gain and large swing. Common-mode feedback circuits (CMFB), which contain five transistors OTA and sensing resistors, are used to set the first-stage output to a known value. The designed two-stage telescopic operational amplifier has 41.04[Formula: see text]dB lower frequency gain, 1.81[Formula: see text]GHz gain-bandwidth product (GBW) and 51.9∘ phase margin under 5[Formula: see text]pF load capacitance. The design consumes a total current of 11.9[Formula: see text]mA from a 1.2-V supply voltage. Presented fully differential two-stage telescopic op-amp by using low-voltage design techniques is suitable for active filter in vehicle-to-everything (V2X) applications with 120[Formula: see text][Formula: see text]m[Formula: see text]m layout area.

scholarly journals Comparative analysis of SRAM cell with leakage power reduction approaches

2018 ◽  
Vol 7 (2.7) ◽  
pp. 863
Author(s):  
Damarla Paradhasaradhi ◽  
Kollu Jaya Lakshmi ◽  
Yadavalli Harika ◽  
Busa Ravi Teja Sai ◽  
Golla Jayanth Krishna
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Low Voltage ◽  
Power Saving ◽  
Vital Role ◽  
Power Reduction ◽  
Leakage Power ◽  
Access Time ◽  
Chip Area ◽  
Sram Cell

In deep sub-micron technologies, high number of transistors is mounted onto a small chip area where, SRAM plays a vital role and is considered as a major part in many VLSI ICs because of its large density of storage and very less access time. Due to the demand of low power applications the design of low power and low voltage memory is a demanding task. In these memories majority of power dissipation depends on leakage power. This paper analyzes the basic 6T SRAM cell operation. Here two different leakage power reduction approaches are introduced to apply for basic 6T SRAM. The performance analysis of basic SRAM cell, SRAM cell using drowsy-cache approach and SRAM cell using clamping diode are designed at 130nm using Mentor Graphics IC Studio tool. The proposed SRAM cell using clamping diode proves to be a better power reduction technique in terms of power as compared with others SRAM structures. At 3.3V, power saving by the proposed SRAM cell is 20% less than associated to basic 6T SRAM Cell.

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