Technique for Compensation of Temperature Drift in Thermal Excited Si-Based Resonant Pressure Sensor

2011 ◽  
Vol 483 ◽  
pp. 224-227 ◽  
Author(s):  
Zheng Yuan Zhang ◽  
Yong Mei ◽  
Jian Gen Li ◽  
Xiao Gang Li ◽  
Zhi Cheng Feng

A Si-based resonant pressure sensor structure with dual-beam was proposed to solve the problem of serious temperature drift in thermal excited Si-based resonant pressure sensor. In this structure, temperature variation sensed by non-pressure-sensing resonant beam was subtracted from that sensed by pressure-sensing beam, to cancel variations of the pressure-sensing beam with temperature and compensate for temperature drift of thermal-excited Si-based resonant pressure sensor. A prototype of Si-based resonant pressure sensor with dual-beam was developed. Preliminary test results showed that the effect of temperature drift was reduced to 1/30 of the uncompensated device, greatly improving sensing accuracy of thermal excited Si-based resonant pressure sensor.

2020 ◽  
Vol 4 (1) ◽  
pp. 27
Author(s):  
Ridwan Yusuf Lubis ◽  
Lailatul Husna Lubis ◽  
Miftahul Husnah

Author(s):  
Steven B. Herschbein ◽  
Hyoung H. Kang ◽  
Scott L. Jansen ◽  
Andrew S. Dalton

Abstract Test engineers and failure analyst familiar with random access memory arrays have probably encountered the frustration of dealing with address descrambling. The resulting nonsequential internal bit cell counting scheme often means that the location of the failing cell under investigation is nowhere near where it is expected to be. A logical to physical algorithm for decoding the standard library block might have been provided with the design, but is it still correct now that the array has been halved and inverted to fit the available space in a new processor chip? Off-line labs have traditionally been tasked with array layout verification. In the past, hard and soft failures could be induced on the frontside of finished product, then bitmapped to see if the sites were in agreement. As density tightened, flip-chip FIB techniques to induce a pattern of hard fails on packaged devices came into practice. While the backside FIB edit method is effective, it is complex and expensive. The installation of an in-line Dual Beam FIB created new opportunities to move FA tasks out of the lab and into the FAB. Using a new edit procedure, selected wafers have an extensive pattern of defects 'written' directly into the memory array at an early process level. Bitmapping of the RAM blocks upon wafer completion is then used to verify correlation between the physical damaged cells and the logical sites called out in the test results. This early feedback in-line methodology has worked so well that it has almost entirely displaced the complex laboratory procedure of backside FIB memory array descramble verification.


2020 ◽  
Vol 8 (4) ◽  
pp. 296-307
Author(s):  
Konstantin Krestovnikov ◽  
Aleksei Erashov ◽  
Аleksandr Bykov

This paper presents development of pressure sensor array with capacitance-type unit sensors, with scalable number of cells. Different assemblies of unit pressure sensors and their arrays were considered, their characteristics and fabrication methods were investigated. The structure of primary pressure transducer (PPT) array was presented; its operating principle of array was illustrated, calculated reference ratios were derived. The interface circuit, allowing to transform the changes in the primary transducer capacitance into voltage level variations, was proposed. A prototype sensor was implemented; the dependency of output signal power from the applied force was empirically obtained. In the range under 30 N it exhibited a linear pattern. The sensitivity of the array cells to the applied pressure is in the range 134.56..160.35. The measured drift of the output signals from the array cells after 10,000 loading cycles was 1.39%. For developed prototype of the pressure sensor array, based on the experimental data, the average signal-to-noise ratio over the cells was calculated, and equaled 63.47 dB. The proposed prototype was fabricated of easily available materials. It is relatively inexpensive and requires no fine-tuning of each individual cell. Capacitance-type operation type, compared to piezoresistive one, ensures greater stability of the output signal. The scalability and adjustability of cell parameters are achieved with layered sensor structure. The pressure sensor array, presented in this paper, can be utilized in various robotic systems.


Soft Matter ◽  
2021 ◽  
Vol 17 (10) ◽  
pp. 2942-2956
Author(s):  
Rishabh D. Guha ◽  
Ogheneovo Idolor ◽  
Katherine Berkowitz ◽  
Melissa Pasquinelli ◽  
Landon R. Grace

We investigated the effect of temperature variation on the secondary bonding interactions between absorbed moisture and epoxies with different morphologies using molecular dynamics simulations.


2013 ◽  
Vol 647 ◽  
pp. 315-320 ◽  
Author(s):  
Pradeep Kumar Rathore ◽  
Brishbhan Singh Panwar

This paper reports on the design and optimization of current mirror MOSFET embedded pressure sensor. A current mirror circuit with an output current of 1 mA integrated with a pressure sensing n-channel MOSFET has been designed using standard 5 µm CMOS technology. The channel region of the pressure sensing MOSFET forms the flexible diaphragm as well as the strain sensing element. The piezoresistive effect in MOSFET has been exploited for the calculation of strain induced carrier mobility variation. The output transistor of the current mirror forms the active pressure sensing MOSFET which produces a change in its drain current as a result of altered channel mobility under externally applied pressure. COMSOL Multiphysics is utilized for the simulation of pressure sensing structure and Tspice is employed to evaluate the characteristics of the current mirror pressure sensing circuit. Simulation results show that the pressure sensor has a sensitivity of 10.01 mV/MPa. The sensing structure has been optimized through simulation for enhancing the sensor sensitivity to 276.65 mV/MPa. These CMOS-MEMS based pressure sensors integrated with signal processing circuitry on the same chip can be used for healthcare and biomedical applications.


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