Advances for Enhanced GaN-Based HEMT Devices with p-GaN Gate

2020 ◽  
Vol 1014 ◽  
pp. 75-85
Author(s):  
Min Zhong ◽  
Ying Xi Niu ◽  
Hai Ying Cheng ◽  
Chen Xi Yan ◽  
Zhi Yuan Liu ◽  
...  
Keyword(s):  
High Speed ◽  
Rf Circuits ◽  
Digital Circuit ◽  
Process Technology ◽  
Device Structure ◽  
Power Characteristics ◽  
Channel Current ◽  
Gan Hemt ◽  
Gate Structure ◽  
Recessed Gate

With the development of high-voltage switches and high-speed RF circuits, the enhancement mode(E-mode) AlGaN/GaN HEMTs have become a hot topic in those fields. The E-mode GaN-based HEMTs have channel current at the positive gate voltage, greatly expanding the device in low power digital circuit applications. The main methods to realize E-mode AlGaN/GaN HEMT power devices are p-GaN gate technology, recessed gate structure, fluoride ion implantation technology and Cascode structure (Cascode). In this paper, the advantage and main realizable methods of E-mode AlGaN/GaN HEMT are briefly described. The research status and problems of E-mode AlGaN/GaN HEMT devices fabricated by p-GaN gate technology are summarized. The advances of p-GaN gate technology, and focuses on how these research results can improve the power characteristics and reliability of E-mode AlGaN/GaN HEMT by optimizing device structure and improving process technology, are discussed.

scholarly journals A Low-Power 12-Bit 20 MS/s Asynchronously Controlled SAR ADC for WAVE ITS Sensor Based Applications

Sensors ◽  
2021 ◽  
Vol 21 (7) ◽  
pp. 2260
Author(s):  
Khuram Shehzad ◽  
Deeksha Verma ◽  
Danial Khan ◽  
Qurat Ul Ain ◽  
Muhammad Basim ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Intelligent Transportation System ◽  
Cmos Process ◽  
Process Technology ◽  
Back Issue ◽  
Digital To Analog Converter ◽  
Analog To Digital ◽  
Switching Method

A low power 12-bit, 20 MS/s asynchronously controlled successive approximation register (SAR) analog-to-digital converter (ADC) to be used in wireless access for vehicular environment (WAVE) intelligent transportation system (ITS) sensor based application is presented in this paper. To optimize the architecture with respect to power consumption and performance, several techniques are proposed. A switching method which employs the common mode charge recovery (CMCR) switching process is presented for capacitive digital-to-analog converter (CDAC) part to lower the switching energy. The switching technique proposed in our work consumes 56.3% less energy in comparison with conventional CMCR switching method. For high speed operation with low power consumption and to overcome the kick back issue in the comparator part, a mutated dynamic-latch comparator with cascode is implemented. In addition, to optimize the flexibility relating to the performance of logic part, an asynchronous topology is employed. The structure is fabricated in 65 nm CMOS process technology with an active area of 0.14 mm2. With a sampling frequency of 20 MS/s, the proposed architecture attains signal-to-noise distortion ratio (SNDR) of 65.44 dB at Nyquist frequency while consuming only 472.2 µW with 1 V power supply.

scholarly journals Physics-Based TCAD Simulation and Calibration of 600 V GaN/AlGaN/GaN Device Characteristics and Analysis of Interface Traps

Micromachines ◽  
2021 ◽  
Vol 12 (7) ◽  
pp. 751
Author(s):  
Yu-Lin Song ◽  
Manoj Kumar Reddy ◽  
Luh-Maan Chang ◽  
Gene Sheu
Keyword(s):  
Conduction Band ◽  
Computer Aided Design ◽  
Measurement Data ◽  
High Electron Mobility Transistor ◽  
High Electron ◽  
Device Structure ◽  
Gan Hemt ◽  
Fixed Charges ◽  
Vertical Electric Field ◽  
Aided Design

This study proposes an analysis of the physics-based TCAD (Technology Computer-Aided Design) simulation procedure for GaN/AlGaN/GaN HEMT (High Electron Mobility Transistor) device structures grown on Si (111) substrate which is calibrated against measurement data. The presence of traps and activation energies in the device structure will impact the performance of a device, the source of traps and position of traps in the device remains as a complex exercise until today. The key parameters for the precise tuning of threshold voltage (Vth) in GaN transistors are the control of the positive fixed charges −5 × 1012 cm−2, donor-like traps −3 × 1013 cm−2 at the nitride/GaN interfaces, the energy of the donor-like traps 1.42 eV below the conduction band and the acceptor traps activation energy in the AlGaN layer and buffer regions with 0.59 eV below the conduction band. Hence in this paper, the sensitivity of the trap mechanisms in GaN/AlGaN/GaN HEMT transistors, understanding the absolute vertical electric field distribution, electron density and the physical characteristics of the device has been investigated and the results are in good agreement with GaN experimental data.

High transconductance AlGaN/GaN-HEMT with recessed gate on sapphire substrate

2003 ◽  
Vol 200 (1) ◽  
pp. 187-190 ◽  
Author(s):  
Hideyuki Okita ◽  
Katsuaki Kaifu ◽  
Juro Mita ◽  
Tomoyuki Yamada ◽  
Yoshiaki Sano ◽  
...  
Keyword(s):  
Sapphire Substrate ◽  
Gan Hemt ◽  
High Transconductance ◽  
Recessed Gate

Normally-off GaN MIS-HEMT using a combination of recessed-gate structure and CF4plasma treatment

2015 ◽  
Vol 212 (5) ◽  
pp. 1170-1173 ◽  
Author(s):  
Youngrak Park ◽  
Jungjin Kim ◽  
Woojin Chang ◽  
Dongyun Jung ◽  
Sungbum Bae ◽  
...  
Keyword(s):  
Gate Structure ◽  
Recessed Gate

Normally-off AlGaN/AlN/GaN HEMT with a composite recessed gate

2021 ◽  
pp. 107064
Author(s):  
Jialin Li ◽  
Yian Yin ◽  
Ni Zeng ◽  
Fengbo Liao ◽  
Mengxiao Lian ◽  
...  
Keyword(s):  
Gan Hemt ◽  
Recessed Gate

scholarly journals Simulation and experimental investigation of recessed-gate AlGaN/GaN HEMT

2009 ◽  
Vol 58 (3) ◽  
pp. 1966
Author(s):  
Wang Chong ◽  
Quan Si ◽  
Zhang Jin-Feng ◽  
Hao Yue ◽  
Feng Qian ◽  
...  
Keyword(s):  
Experimental Investigation ◽  
Gan Hemt ◽  
Recessed Gate

scholarly journals Performance Analysis of a Low Power High Speed Hybrid Full Adder Circuit and Full Subtractor Circuit

2021 ◽  
Vol 12 (3) ◽  
pp. 3037-3045
Author(s):  
M. Naga Gowtham Et.al
Keyword(s):  
High Speed ◽  
Supply Voltage ◽  
Average Power ◽  
Full Adder ◽  
Digital Circuit ◽  
Oxide Semiconductor ◽  
Transmission Gate ◽  
Average Power Consumption ◽  
Pass Transistor ◽  
Pass Transistor Logic

In this paper, a hybrid 1-bit adder and 1-bit Subtractor designs are implemented. The hybrid adder circuit is constructed using CMOS (complementary metal oxide semiconductor) logic along with pass transistor logic. The design can be extended 16 and 32 bits lately. The proposed full adder circuit is compared with the existing conventional adders in terms of power, delay and area in order to obtain a better circuit that serves the present day needs of people. The existing 1-bit hybrid adder uses EXNOR logic combined with the transmission gate logic. For a supply voltage of 1.8V the average power consumption (4.1563 µW) which is extremely low with moderately low delay (224 ps) resulting because of the deliberate incorporation of very weak CMOS inverters coupled with strong transmission gates. At 1.2V supply the power and delay were recorded to be 1.17664 µW and 91.3 ps. The design was implemented using 1-bit which can also be extended into a 32-bit design later. The designed implementation offers a better performance in terms of power and speed compared to the existing full adder design styles. The circuits were implemented in DSCH2 and Microwind tools respectively. The parameters such as power, delay, layout area and speed of the proposed circuit design is compared with pass transistor logic, adiabatic logic, transmission gate adder and so on. The circuit is also designed with a decrease in transistors in order to get the better results. Full Subtractor, a combinational digital circuit which performs 1-bit subtraction with borrow in is designed as a part of this project. The main aim behind this part of the project is to design a 1-bit full Subtractor using CMOS technology with reduced number of transistors and hence the efficiency in terms of area, power and speed have been calculated is designed using 8,10,15and 16 transistors. The parameters were calculated in each case and the results have been tabulated.

scholarly journals Novel Design of Low-Power High-Speed Hybrid Full Adder Design using Gate Diffusion Input (GDI) Technique

2020 ◽  
Vol 9 (12) ◽  
pp. 323-328
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Critical Path ◽  
Circuit Simulation ◽  
Full Adder ◽  
Cmos Process ◽  
Path Delay ◽  
Process Technology ◽  
Xnor Gate

VLSI technology become one of the most significant and demandable because of the characteristics like device portability, device size, large amount of features, expenditure, consistency, rapidity and many others. Multipliers and Adders place an important role in various digital systems such as computers, process controllers and signal processors in order to achieve high speed and low power. Two input XOR/XNOR gate and 2:1 multiplexer modules are used to design the Hybrid Full adders. The XOR/XNOR gate is the key punter of power included in the Full adder cell. However this circuit increases the delay, area and critical path delay. Hence, the optimum design of the XOR/XNOR is required to reduce the power consumption of the Full adder Cell. So a 6 New Hybrid Full adder circuits are proposed based on the Novel Full-Swing XOR/XNOR gates and a New Gate Diffusion Input (GDI) design of Full adder with high-swing outputs. The speed, power consumption, power delay product and driving capability are the merits of the each proposed circuits. This circuit simulation was carried used cadence virtuoso EDA tool. The simulation results based on the 90nm CMOS process technology model.

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