Reliability of Sn-Ag-Cu Flip Chip Package with Underfill under Thermal Shock

2006 ◽  
Vol 510-511 ◽  
pp. 558-561 ◽  
Author(s):  
Bo In Noh ◽  
Seung Boo Jung
Keyword(s):  
Thermal Expansion ◽  
Thermal Shock ◽  
Solder Ball ◽  
Flip Chip ◽  
Coefficient Of Thermal Expansion ◽  
Fatigue Property ◽  
Electroless Nickel ◽  
Fatigue Properties ◽  
Electroless Nickel Immersion Gold ◽  
Better Than

Thermal fatigue properties of solder joints encapsulated with underfill were studied conducting thermal shock tests. Flip chip package with electroless nickel-immersion gold plated on FR-4 substrate and the Sn-3.0Ag-0.5Cu solder ball was used. The fatigue property of package with underfill was better than the package without it. The fatigue property of package with underfill which has a higher glass transition temperature (Tg) and lower coefficient of thermal expansion (CTE) was better than that of package with underfill with lower Tg and higher CTE.

Reliability of Flip Chip Package with Underfills under Thermal Shock

2006 ◽  
Vol 321-323 ◽  
pp. 1719-1722
Author(s):  
Bo In Noh ◽  
Seung Boo Jung
Keyword(s):  
Thermal Shock ◽  
Thermal Fatigue ◽  
Flip Chip ◽  
Coefficient Of Thermal Expansion ◽  
Fatigue Property ◽  
Electroless Nickel ◽  
Fatigue Properties ◽  
Thermal Shock Test ◽  
Thermal Fatigue Crack ◽  
Better Than

The thermal fatigue properties of the solder joints with various underfills were evaluated by thermal shock test. Flip chip package with electroless nickel-immersion gold plated on Cu pad of FR-4 substrate and the Sn-37Pb solder ball was used. The thermal fatigue crack initiated at the edges of interface between solder and silicon die. The fatigue property of package with underfill, which has a higher glass transition temperature (Tg) and lower coefficient of thermal expansion (CTE) value was better than that of package with underfill having a lower Tg and higher CTE.

Application of an Epoxy Cap in a Flip-Chip Package Design

1989 ◽  
Vol 111 (1) ◽  
pp. 16-20 ◽  
Author(s):  
E. Suhir
Keyword(s):  
Thermal Expansion ◽  
Flip Chip ◽  
Coefficient Of Thermal Expansion ◽  
Preliminary Test ◽  
Elastic Stability ◽  
Thermally Induced ◽  
Package Design ◽  
Silicone Gels ◽  
Low Modulus ◽  
Supporting Frame

In order to combine the merits of epoxies, which provide good environmental and mechanical protection, and the merits of silicone gels, resulting in low stresses, one can use an encapsulation version, where a low modulus gel is utilized as a major encapsulant, while epoxy is applied as a protecting cap. Such an encapsulation version is currently under consideration, parallel with a metal cap version, for the Advanced VLSI package design which is being developed at AT&T Bell Laboratories. We recommend that the coefficient of thermal expansion for the epoxy be somewhat smaller than the coefficient of thermal expansion for the supporting frame. In this case the thermally induced displacements would result in a desirable tightness in the cap/frame interface. This paper is aimed at the assessment of stresses, which could arise in the supporting frame and in the epoxy cap at low temperatures. Also, the elastic stability of the cap, subjected to compression, is evaluated. The calculations were executed for the Advanced VLSI package design and for a Solder Test Vehicle (STV), which is currently used to obtain preliminary information regarding the performance of the candidate encapsulants. It is concluded that in order to avoid buckling of the cap, the latter should not be thinner than 15 mils (0.40 mm) in the case of VLSI package design and than 17.5 mils (0.45 mm) in the case of STV. At the same time, the thickness of the cap should not be greater than necessary, both for smaller stresses in the cap and for sufficient undercap space, required for wirebond encapsulation. The obtained formulas enable one to evaluate the actual and the buckling stresses. Preliminary test data, obtained by using STV samples, confirmed the feasibility of the application of an epoxy cap in a flip-chip package design.

Electrical conductivity changes in bulk Sn, and eutectic Sn-Ag in bulk and in joints, from aging and thermal shock

2005 ◽  
Vol 20 (2) ◽  
pp. 364-374 ◽  
Author(s):  
F. Guo ◽  
J.G. Lee ◽  
T. Hogan ◽  
K.N. Subramanian
Keyword(s):  
Electrical Conductivity ◽  
Thermal Expansion ◽  
Thermal Shock ◽  
Intermetallic Compounds ◽  
Damage Accumulation ◽  
Coefficient Of Thermal Expansion ◽  
Substrate Interface ◽  
Effects Of Aging

Electrical conductivity of electronic interconnects made with Sn-based solders undergo a significant amount of deterioration during service. Several factors, such as anisotropy of Sn, coefficient of thermal expansion mismatches between the entities that make up the joint, and growth of intermetallic compounds present within the solder and solder/substrate interface, may contribute to the damage accumulation during thermal excursions and cause deterioration of properties. This study dealing with effects of aging and thermal shock on electrical conductivity, carried out with bulk Sn, and eutectic Sn–Ag in bulk and joint configurations, is aimed at evaluating the roles of the above factors on the deterioration of electrical conductivity from these thermal excursions.

Quantitative Bump Height Analysis in ENIG Using Design of Experiment

2014 ◽  
Vol 896 ◽  
pp. 660-663
Author(s):  
Zaliman Sauli ◽  
Vithyacharan Retnasamy ◽  
Phaklen Ehkan ◽  
Fairul Afzal Ahmad Fuad ◽  
Aaron Koay Terr Yeow
Keyword(s):  
Design Of Experiment ◽  
Flip Chip ◽  
Electroless Nickel ◽  
Bump Height ◽  
Process Robustness ◽  
Electroless Nickel Immersion Gold ◽  
Optimization Of Process Parameters ◽  
Chip Technology ◽  
Higher Temperature

Flip chip technology has grown by leaps and bounds and is getting even smaller in size. Optimization of process parameters in manufacturing is eminent due to reliability issues. This paper reports the parameters that affect the quality of the bump height in electroless nickel immersion gold (ENIG) and their relationships between each other. A total of four different combinations of parameters have been carried out for this investigation using the design of experiment (DOE) approach. It can be concluded that higher temperature of electroless nickel permits an increase of bump height where as the increment in immersion gold temperature does not nessasarily affect the value of bump height. All four samples recorded a higher value of bump height than the controlled bump height value. This implies reliability of the solder joint and assembly process robustness can be improved with an increase of bump height by increasing the time.

Design and fabrication of MEMS-type compliant overhang flip-chip interconnect for RF applications

2015 ◽  
Vol 2015 (DPC) ◽  
pp. 002082-002094
Author(s):  
Pingye Xu ◽  
Michael C. Hamilton
Keyword(s):  
Solder Ball ◽  
Flip Chip ◽  
Coefficient Of Thermal Expansion ◽  
Organic Substrate ◽  
Process Temperature ◽  
High Yield ◽  
Wafer Level ◽  
Micro Fabrication ◽  
Compliant Interconnect ◽  
Sac Solder

With the increase of I/O density and scaling of interconnects, conventional solder ball interconnects are required to be made smaller. As a result, the reliability of the conventional solder ball flip-chip interconnects worsens. One method to mitigate this issue is by using underfill. However, underfill undermines the reworkability of the solder joints and is challenging to apply when the gap between chip and substrate is small. Another approach to enhance the reliability is to use taller solder ball interconnects, which is however usually more costly. Instead of using conventional solder ball interconnects, compliant interconnects have also been researched in the past few decades to mitigate the reliability issue. The use of compliant structures can compensate for the coefficient of thermal expansion (CTE) mismatch between a Si chip and an organic substrate. In this work, we present the design and fabrication of MEMS-type compliant overhang flip-chip interconnects. The structures are placed at the end of a coplanar waveguide (CPW) as interconnects between CPWs to research their performance at radio frequency (RF). A micro-fabrication process was adopted to build the interconnects. The CPWs are fabricated using conventional e-beam deposition followed by photolithography and then copper electroplating. The compliant overhangs were fabricated on top of a dome of reflowed photoresist on the CPWs to form a curved shape. The reflow and hard bake of the photoresist requires a process temperature of above 220 °C, which is similar to the reflow temperature of a Sn-Ag-Cu (SAC) solder. Therefore we believe our process is compatible with SAC solder processing infrastructures in terms of process temperature. The fabricated structures show high yield and uniformity. Due to the use of a micro-fabrication based process, the structures have the potential to be scaled and be compatible to wafer level packaging. The CPWs were then flip-chip bonded with the compliant interconnect as transitions. The RF performance of the interconnects up to 50 GHz will be presented.

Characterization of Epoxy-Functionalized Silsesquioxanes as Potential Underfill Encapsulants

1998 ◽  
Vol 519 ◽  
Author(s):  
E. K. Lin ◽  
C. R. Snyder ◽  
F. I. Mopsik ◽  
W. E. Wallace ◽  
W. L. Wu ◽  
...  
Keyword(s):  
Thermal Expansion ◽  
Flip Chip ◽  
Coefficient Of Thermal Expansion ◽  
Silica Particles ◽  
Critical Parameters ◽  
Organic Hybrid ◽  
Solder Bumps ◽  
The Difference ◽  
Electronics Packages

AbstractIn electronics packaging, underfill encapsulants are needed to improve package reliability in flip-chip devices. The underfill generally consists of an epoxy resin highly filled with silica particles and is designed to reduce the stress arising from the difference in the thermal expansion between the solder bumps and the substrate. Currently, concerns about the flow of the silica particles and surface phenomena are arising as electronics packages reduce in size. Newly developed epoxy-functionalized octameric silsesquioxanes provide an intriguing alternative to current formulations. These single-phase inorganic/organic hybrid materials may have properties similar to filled materials without the complications from the rheology of filled materials. The physical properties of the functionalized silsesquioxanes are measured with respect to the critical parameters for underfill materials. Measurements of properties such as the coefficient of thermal expansion and density are performed to evaluate the suitability of these materials as potential underfill encapsulants.

Mechanical reliability of Cu cored solder ball in flip chip package under thermal shock test

2020 ◽  
Vol 112 ◽  
pp. 113918
Author(s):  
Haksan Jeong ◽  
Kyung Deuk Min ◽  
Choong-Jae Lee ◽  
Jae-Ha Kim ◽  
Seung-Boo Jung
Keyword(s):  
Thermal Shock ◽  
Solder Ball ◽  
Flip Chip ◽  
Thermal Shock Test ◽  
Mechanical Reliability ◽  
Shock Test

scholarly journals Intrinsic Thermal Shock Behavior of Common Rutile Oxides

Physics ◽  
2019 ◽  
Vol 1 (2) ◽  
pp. 290-300 ◽  
Author(s):  
Denis Music ◽  
Bastian Stelzer
Keyword(s):  
Thermal Conductivity ◽  
Thermal Expansion ◽  
Elastic Modulus ◽  
Thermal Shock ◽  
Thermal Shock Resistance ◽  
Density Functional ◽  
Coefficient Of Thermal Expansion ◽  
Thermomechanical Properties ◽  
Linear Coefficient ◽  
Shock Resistance

Rutile TiO2, VO2, CrO2, MnO2, NbO2, RuO2, RhO2, TaO2, OsO2, IrO2, SnO2, PbO2, SiO2, and GeO2 (space group P42/mnm) were explored for thermal shock resistance applications using density functional theory in conjunction with acoustic phonon models. Four relevant thermomechanical properties were calculated, namely thermal conductivity, Poisson’s ratio, the linear coefficient of thermal expansion, and elastic modulus. The thermal conductivity exhibited a parabolic relationship with the linear coefficient of thermal expansion and the extremes were delineated by SiO2 (the smallest linear coefficient of thermal expansion and the largest thermal conductivity) and PbO2 (vice versa). It is suggested that stronger bonding in SiO2 than PbO2 is responsible for such behavior. This also gave rise to the largest elastic modulus of SiO2 in this group of rutile oxides. Finally, the intrinsic thermal shock resistance was the largest for SiO2, exceeding some of the competitive phases such as Al2O3 and nanolaminated Ti3SiC2.

Numerical and Experimental Study of Interface Delamination in Flip Chip BGA Package

2010 ◽  
Vol 132 (1) ◽  
Author(s):  
Hu Guojun ◽  
Andrew A. O. Tay ◽  
Luan Jing-En ◽  
Ma Yiyi
Keyword(s):  
Thermal Expansion ◽  
Material Properties ◽  
Flip Chip ◽  
Coefficient Of Thermal Expansion ◽  
Element Analysis ◽  
Epoxy Molding Compound ◽  
Molding Compound ◽  
Interface Delamination ◽  
Underfill Material ◽  
Die Thickness

The reliability of the flip chip package is strongly influenced by underfill, which has a much higher coefficient of thermal expansion (CTE) compared with other packaging materials and leads to large thermomechanical stresses developed during the assembly processes. Thermal expansion mismatch between different materials causes interface delamination between epoxy molding compound and silicon die as well as interface delamination between underfill and silicon die. The main objective of this study is to investigate the effects of underfill material properties, fillet height, and silicon die thickness on the interface delamination between epoxy molding compound and silicon die during a lead-free solder reflow process based on the modified virtual crack closure method. Based on finite element analysis and experiment study, it can be concluded that the energy release rates at reflow temperature are the suitable criteria for the estimation of interface delamination. Furthermore, it is found that underfill material properties (elastic modulus, CTE, and chemical cure shrinkage), fillet height, and silicon die thickness can be optimized to reduce the risk of interface delamination between epoxy molding compound and silicon die in the flip chip ball grid array package.

INCOLOY ALLOY 909

Alloy Digest ◽  
1987 ◽  
Vol 36 (12) ◽  
Keyword(s):  
Thermal Expansion ◽  
Corrosion Resistance ◽  
Physical Properties ◽  
Thermal Shock ◽  
Thermal Fatigue ◽  
Coefficient Of Thermal Expansion ◽  
High Strength ◽  
Heat Treating ◽  
Strength Alloy ◽  
Incoloy Alloy

Abstract INCOLOY alloy 909 is a high-strength alloy having a constant low coefficient of thermal expansion and an essentially constant rigidity up to 1200 F. The alloy is highly resistant to thermal fatigue and thermal shock. This datasheet provides information on composition, physical properties, elasticity, and tensile properties. It also includes information on corrosion resistance as well as forming, heat treating, machining, and joining. Filing Code: Fe-81. Producer or source: Inco Alloys International Inc..

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