Quantitative Bump Height Analysis in ENIG Using Design of Experiment

2014 ◽  
Vol 896 ◽  
pp. 660-663
Author(s):  
Zaliman Sauli ◽  
Vithyacharan Retnasamy ◽  
Phaklen Ehkan ◽  
Fairul Afzal Ahmad Fuad ◽  
Aaron Koay Terr Yeow
Keyword(s):  
Design Of Experiment ◽  
Flip Chip ◽  
Electroless Nickel ◽  
Bump Height ◽  
Process Robustness ◽  
Electroless Nickel Immersion Gold ◽  
Optimization Of Process Parameters ◽  
Chip Technology ◽  
Higher Temperature

Flip chip technology has grown by leaps and bounds and is getting even smaller in size. Optimization of process parameters in manufacturing is eminent due to reliability issues. This paper reports the parameters that affect the quality of the bump height in electroless nickel immersion gold (ENIG) and their relationships between each other. A total of four different combinations of parameters have been carried out for this investigation using the design of experiment (DOE) approach. It can be concluded that higher temperature of electroless nickel permits an increase of bump height where as the increment in immersion gold temperature does not nessasarily affect the value of bump height. All four samples recorded a higher value of bump height than the controlled bump height value. This implies reliability of the solder joint and assembly process robustness can be improved with an increase of bump height by increasing the time.

Relationship between Controllable Process Parameters on Bump Height in ENIG

2013 ◽  
Vol 404 ◽  
pp. 62-66
Author(s):  
Zaliman Sauli ◽  
Vithyacharan Retnasamy ◽  
Fairul Afzal Ahmad Fuad ◽  
Phaklen Ehkan ◽  
Muhamad Hafiz Ab Aziz
Keyword(s):  
Process Parameters ◽  
Design Of Experiment ◽  
Electroless Nickel ◽  
Critical Issue ◽  
Process Variables ◽  
Soldering Process ◽  
Bump Height ◽  
Electroless Nickel Immersion Gold ◽  
Controllable Process

This paper reports the factors that affect the bump height in electroless nickel immersion gold (ENIG) and their interrelation between each other. Bump height is a critical issue that needs to be investigated because a certain quality and requirements of bump height needs to be achieved prior to reflow oven soldering process. A total of four controllable process variables, with 16 sets of experiments were studied using a systematically designed design of experiment (DOE). The result suggests that the electroless nickel bath time has the most significant effect on the formation on bump height and consequently provide larger area for conductivity.

Chemical Bath Temperature Investigation for Electroless Nickel Immersion Gold

2014 ◽  
Vol 925 ◽  
pp. 96-100
Author(s):  
Vithyacharan Retnasamy ◽  
Zaliman Sauli ◽  
Uda Hashim ◽  
Aaron Koay Terr Yeow ◽  
Steven Taniselass ◽  
...  
Keyword(s):  
Electroless Nickel ◽  
Bath Temperature ◽  
Gold Wire ◽  
Process Time ◽  
Reflow Process ◽  
Bump Height ◽  
Electroless Nickel Immersion Gold ◽  
Solder Bumps ◽  
Higher Temperature ◽  
Bond Pads

Conventional gold wire bonding to alunimium bond pads leads to the formation of intermetallic compound. Electroless Nickel Immersion Gold (ENIG) has been proposed as surface finish for aluminium bond pads to improve high temperature reliability. In order to create acceptable solder bumps prior to reflow process, a particular bump height for ENIG bumps need to be obtained. This paper reports the effects of chemical bath temperature in response to the bump height using a shorter process time. Analysis was done by using a design of experiment (DOE). The results suggest that higher temperature increases the bump height. Electroless nickel temperature has more influence to the bump height compared to immersion gold temperature.

Reliability of Sn-Ag-Cu Flip Chip Package with Underfill under Thermal Shock

2006 ◽  
Vol 510-511 ◽  
pp. 558-561 ◽  
Author(s):  
Bo In Noh ◽  
Seung Boo Jung
Keyword(s):  
Thermal Expansion ◽  
Thermal Shock ◽  
Solder Ball ◽  
Flip Chip ◽  
Coefficient Of Thermal Expansion ◽  
Fatigue Property ◽  
Electroless Nickel ◽  
Fatigue Properties ◽  
Electroless Nickel Immersion Gold ◽  
Better Than

Thermal fatigue properties of solder joints encapsulated with underfill were studied conducting thermal shock tests. Flip chip package with electroless nickel-immersion gold plated on FR-4 substrate and the Sn-3.0Ag-0.5Cu solder ball was used. The fatigue property of package with underfill was better than the package without it. The fatigue property of package with underfill which has a higher glass transition temperature (Tg) and lower coefficient of thermal expansion (CTE) was better than that of package with underfill with lower Tg and higher CTE.

Bumping Co-planarity Collocation for Different UBM Size by Geometry Integration

2019 ◽  
Vol 2019 (1) ◽  
pp. 000476-000479
Author(s):  
Wei-Wei (Xenia) Liu ◽  
Berdy Weng ◽  
Lu-Ming Lai ◽  
Kuang-Hsiung Chen
Keyword(s):  
Flip Chip ◽  
Process Window ◽  
Height Variation ◽  
Bump Height ◽  
Cu Pillar ◽  
Cu Pillar Bump ◽  
Solder Volume ◽  
Joint Quality ◽  
Oval Shape

Abstract Bumping co-planarity is a Cu pillar bump characteristic, that can impact to the joint quality of subsequent flip chip bonding process. The plated bump height variation correlates with lesser co-planarity values. Co-planarity can be minimized by bumping process, however the bumping process window is not adequate for some design features. For example, dummy bump or structure drawback features. This paper provides a methodology to improve co-planarity by collocating oval and circular bump which integrates the solder volume of different bump shapes. The final solder formation is different due to the geometry variation from the oval shape and circular shape. The final solder height can be calculated by mathematical integral from as-plated solder volume. Hence, better co-planarity can be achieved by the proposed method to collocate different bump shapes. The Cu pillar bump collocation design rules can be optimized to minimize co-planarity during initial design realization to minimize quality risks during fabrication..

Thin-Die Flip Chip Physical-FA Process Flow

2002 ◽  
Author(s):  
Andrew J. Komrowski ◽  
N. S. Somcio ◽  
Daniel J. D. Sullivan ◽  
Charles R. Silvis ◽  
Luis Curiel ◽  
...  
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
Flip Chip ◽  
Semiconductor Industry ◽  
Organic Substrate ◽  
Fault Isolation ◽  
Preparation Methods ◽  
Chip Technology ◽  
Isolation Test ◽  
Sample Preparation Methods

Abstract The use of flip chip technology inside component packaging, so called flip chip in package (FCIP), is an increasingly common package type in the semiconductor industry because of high pin-counts, performance and reliability. Sample preparation methods and flows which enable physical failure analysis (PFA) of FCIP are thus in demand to characterize defects in die with these package types. As interconnect metallization schemes become more dense and complex, access to the backside silicon of a functional device also becomes important for fault isolation test purposes. To address these requirements, a detailed PFA flow is described which chronicles the sample preparation methods necessary to isolate a physical defect in the die of an organic-substrate FCIP.

Failure Analysis of Flip-Chip Interconnections Through Acoustic Microscopy

1996 ◽  
Author(s):  
O. Diaz de Leon ◽  
M. Nassirian ◽  
C. Todd ◽  
R. Chowdhury
Keyword(s):  
Failure Analysis ◽  
Large Scale ◽  
Flip Chip ◽  
Ultrasonic Waves ◽  
Acoustic Microscopy ◽  
Acoustic Microscope ◽  
Chip Technology ◽  
Ball Joints ◽  
Non Destructive ◽  
Scanning Acoustic Microscope

Abstract Integration of circuits on semiconductor devices with resulting increase in pin counts is driving the need for improvements in packaging for functionality and reliability. One solution to this demand is the Flip- Chip concept in Ultra Large Scale Integration (ULSI) applications [1]. The flip-chip technology is based on the direct attach principle of die to substrate interconnection.. The absence of bondwires clearly enables packages to become more slim and compact, and also provides higher pin counts and higher-speeds [2]. However, due to its construction, with inherent hidden structures the Flip-Chip technology presents a challenge for non-destructive Failure Analysis (F/A). The scanning acoustic microscope (SAM) has recently emerged as a valuable evaluation tool for this purpose [3]. C-mode scanning acoustic microscope (C-SAM), has the ability to demonstrate non-destructive package analysis while imaging the internal features of this package. Ultrasonic waves are very sensitive, particularly when they encounter density variations at surfaces, e.g. variations such as voids or delaminations similar to air gaps. These two anomalies are common to flip-chips. The primary issue with this package technology is the non-uniformity of the die attach through solder ball joints and epoxy underfill. The ball joints also present defects as open contacts, voids or cracks. In our acoustic microscopy study packages with known defects are considered. It includes C-SCAN analysis giving top views at a particular package interface and a B-SCAN analysis that provides cross-sectional views at a desired point of interest. The cross-section analysis capability gives confidence to the failure analyst in obtaining information from a failing area without physically sectioning the sample and destroying its electrical integrity. Our results presented here prove that appropriate selection of acoustic scanning modes and frequency parameters leads to good reliable correlation between the physical defects in the devices and the information given by the acoustic microscope.

A Sample Preparation on Decapsulation Methodology for Effective Failure Analysis on Thin Small Leadless (TSLP) Flip Chip Package with Copper Pillar (CuP) Bump Interconnect Technology

2014 ◽  
Author(s):  
Gwee Hoon Yen ◽  
Ng Kiong Kay
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
Flip Chip ◽  
Fault Localization ◽  
Cost Effective ◽  
Fault Isolation ◽  
Voltage Contrast ◽  
Interconnect Technology

Abstract Today, failure analysis involving flip chip [1] with copper pillar bump packaging technologies would be the major challenges faced by analysts. Most often, handling on the chips after destructive chemical decapsulation is extremely critical as there are several failure analysis steps to be continued such as chip level fault localization, chip micro probing for fault isolation, parallel lapping [2, 3, 4] and passive voltage contrast. Therefore, quality of sample preparation is critical. This paper discussed and demonstrated a quick, reliable and cost effective methodology to decapsulate the thin small leadless (TSLP) flip chip package with copper pillar (CuP) bump interconnect technology.

scholarly journals Design and Switching Characteristics of Flip-Chip GaN Half-Bridge Modules Integrated with Drivers

2021 ◽  
Vol 11 (15) ◽  
pp. 7057
Author(s):  
Lin Wang ◽  
Zhe Cheng ◽  
Zhi-Guo Yu ◽  
De-Feng Lin ◽  
Zhe Liu ◽  
...  
Keyword(s):  
Flip Chip ◽  
High Electron Mobility Transistors ◽  
Wire Bonding ◽  
High Electron ◽  
Parasitic Inductance ◽  
Switching Performance ◽  
Turn On ◽  
Electron Mobility Transistors ◽  
Chip Technology ◽  
Switching Characteristics

Half-bridge modules with integrated GaN high electron mobility transistors (HEMTs) and driver dies were designed and fabricated in this research. Our design uses flip-chip technology for fabrication, instead of more generally applied wire bonding, to reduce parasitic inductance in both the driver-gate and drain-source loops. Modules were prepared using both methods and the double-pulse test was applied to evaluate and compare their switching characteristics. The gate voltage (Vgs) waveform of the flip-chip module showed no overshoot during the turn-on period, and a small oscillation during the turn-off period. The probabilities of gate damage and false turn-on were greatly reduced. The inductance in the drain-source loop of the module was measured to be 3.4 nH. The rise and fall times of the drain voltage (Vds) were 12.9 and 5.8 ns, respectively, with an overshoot of only 4.8 V during the turn-off period under Vdc = 100 V. These results indicate that the use of flip-chip technology along with the integration of GaN HEMTs with driver dies can effectively reduce the parasitic inductance and improve the switching performance of GaN half-bridge modules compared to wire bonding.

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