Characterisation of 4H-SiC MOS Capacitor with a Protective Coating for Harsh Environments Applications

2017 ◽  
Vol 897 ◽  
pp. 327-330
Author(s):  
Sandip Kumar Roy ◽  
Jesus Urresti Ibanez ◽  
Anthony G. O’Neill ◽  
Nick G. Wright ◽  
Alton B. Horsfall
Keyword(s):  
Silicon Nitride ◽  
High Performance ◽  
Ohmic Contacts ◽  
Surface Characteristics ◽  
Harsh Environments ◽  
Mos Capacitors ◽  
Mos Capacitor ◽  
Mos Devices ◽  
High K ◽  
Mos Structures

Oxygen free Ohmic contacts are essential for the realisation of high performance devices. Ohmic contacts in SiC often require annealing under vacuum at over 1000 °C, whilst high-κ dielectrics are usually annealed in O2 rich ambient at temperatures of 800 °C or less, affecting the electrical and surface characteristics. Therefore, protection of the Ohmic contacts during the annealing of a high-κ dielectric layer is a key enabling step in the realisation of high performance MOS structures. In order to prevent damage during the high-k formation the use of silicon nitride as a passivation layer, capable of protecting the contacts during annealing, has been investigated. In this work we have investigated and compared silicon nitride protected high-κ dielectric SiC based MOS capacitors with the unprotected SiC MOS devices in terms of electrical and optical characteristics.

Characterization of LaxHfyO Gate Dielectrics in 4H-SiC MOS Capacitor

2014 ◽  
Vol 778-780 ◽  
pp. 549-552 ◽  
Author(s):  
Jing Hua Xia ◽  
David M. Martin ◽  
Sethu Saveda Suvanam ◽  
Carl Mikael Zetterling ◽  
Mikael Östling
Keyword(s):  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Atomic Layer ◽  
Deposition Process ◽  
Mos Capacitors ◽  
Mos Capacitor ◽  
Layer Deposition ◽  
High K ◽  
Film Characteristics

LaxHfyO nanolaminated thin film deposited using atomic layer deposition process has been studied as a high-K gate dielectric in 4H-SiC MOS capacitors. The electrical and nano-laminated film characteristics were studied with increasing post deposition annealing (PDA) in N2O ambient. The result shows that high quality LaxHfyO nano-laminated thin films with good interface and bulk qualities are fabricated using high PDA temperature.

Silicon Nitride Encapsulation to Preserve Ohmic Contacts Characteristics in High Temperature, Oxygen Rich Environments

2015 ◽  
Vol 821-823 ◽  
pp. 420-423 ◽  
Author(s):  
Sandip K. Roy ◽  
Konstantin Vassilevski ◽  
Nicholas G. Wright ◽  
Alton B. Horsfall
Keyword(s):  
High Temperature ◽  
Silicon Nitride ◽  
High Performance ◽  
Smooth Surface ◽  
Ohmic Contacts ◽  
Passivation Layer ◽  
Device Performance ◽  
Specific Contact ◽  
Edge Profile ◽  
Specific Contact Resistivity

Ohmic contacts with low contact resistance, smooth surface morphology, and a well-defined edge profile are essential to ensure optimal device performance. Ohmic contacts often require annealing under vacuum at over 1000 °C, whilst high-κ dielectrics are usually annealed in O2rich ambient at temperatures of 800 °C or less, affecting the specific contact resistivity (ρC) and RMS surface roughness. Therefore, protection of the Ohmic contacts during the annealing of a high-κ dielectric layer is a key enabling step in the realisation of high performance MOSFET structures. In order to prevent damage during the high-κ formation, a passivation layer capable of protecting the contacts during annealing is required. In this work we have investigated the suitability of PECVD silicon nitride as a passivation layer to protect Ohmic contacts during high temperature, oxygen rich annealing.

Nonvolatile memory MOS capacitors made of CdSe embedded ZrHfO high-k gate dielectric

2013 ◽  
Vol 1562 ◽  
Author(s):  
Chi-Chou Lin ◽  
Yue Kuo
Keyword(s):  
Gate Voltage ◽  
Coulomb Blockade ◽  
Nonvolatile Memory ◽  
Gate Dielectric ◽  
Stress Test ◽  
Charge Trapping ◽  
Differential Resistance ◽  
Mos Capacitors ◽  
Mos Capacitor ◽  
High K

ABSTRACTMOS capacitor composed of nc-CdSe embedded ZrHfO high-k gate dielectric stack was fabricated and characterized for nonvolatile memory functions. Detailed material and electrical properties have been investigated. With a large charge trapping capability, this kind of device can trap electrons or holes depending on the polarity and magnitude of the applied gate voltage. For the same stress time, the device trapped more holes than electrons under the same magnitude of gate voltage but different polarity. The negative differential resistance peak was observed at the room temperature due to the Coulomb blockade effect. The charge trapping mechanism was delineated with the constant voltage stress test. After 10 years of storage, about 56% of trapped charges still remain in the device.

Effect of Phosphorus Implantation Prior to Oxidation on Electrical Properties of Thermally Grown SiO2/4H-SiC MOS Structures

2014 ◽  
Vol 806 ◽  
pp. 133-138 ◽  
Author(s):  
Aleksey Mikhaylov ◽  
Tomasz Sledziewski ◽  
Alexey Afanasyev ◽  
Victor Luchinin ◽  
Sergey A. Reshanov ◽  
...  
Keyword(s):  
Electrical Properties ◽  
Reference Sample ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Phosphorus Concentration ◽  
Interface Traps ◽  
Mos Capacitor ◽  
Mos Devices ◽  
Dry Oxidation ◽  
Mos Structures

The electrical properties of metal-oxide-semiconductor (MOS) devices fabricated using dry oxidation on phosphorus-implanted n-type 4H-SiC (0001) epilayers have been investigated. MOS structures were compared in terms of interface traps and reliability with reference sample which was produced by dry oxidation under the same conditions. The notably lower interface traps density measured in MOS capacitor with phosphorus concentration exceeding 1018 cm-3 at the SiO2/SiC interface was attributed to interface traps passivation by incorporated phosphorus ions.

scholarly journals Study on the Physical and Leakage Current Characteristics of an Optimized High-k/InAlAs MOS Capacitor with a HfO2–Al2O3 Laminated Dielectric

Coatings ◽  
2018 ◽  
Vol 8 (12) ◽  
pp. 417 ◽  
Author(s):  
He Guan ◽  
Chengyu Jiang
Keyword(s):  
Leakage Current ◽  
High Electron Mobility Transistors ◽  
Oxide Thickness ◽  
Effective Density ◽  
High Electron ◽  
Mos Capacitors ◽  
Mos Capacitor ◽  
New Device ◽  
Conduction Band Offset ◽  
High K

High-k/n-InAlAs MOS capacitors are popular for the isolated gate of InAs/AlSb and InAlAs/InGaAs high-electron mobility transistors. In this study, a new kind of high-k/n-InAlAs MOS-capacitor with a HfO2–Al2O3 laminated dielectric was successfully fabricated using an optimized process. Compared with the traditional HfO2/n-InAlAs MOS capacitor, the new device has a larger equivalent oxide thickness. Two devices, with a HfO2 (8 nm)–Al2O3 (4 nm) laminated dielectric and a HfO2 (4 nm)–Al2O3 (8 nm) laminated dielectric, respectively, were studied in comparison to analyze the effect of the thickness ratios of HfO2 and Al2O3 on the performance of the devices. It was found that the device with a HfO2 (4 nm)–Al2O3 (8 nm) laminated dielectric showed a lower effective density of oxide charges, and an evidently higher conduction band offset, making its leakage current achieve a significantly low value below 10−7 A/cm2 under a bias voltage from −3 to 2 V. It was demonstrated that the HfO2–Al2O3 laminated dielectric with a HfO2 thickness of 4 nm and an Al2O3 thickness of 8 nm improves the performance of the high-k dielectric on InAlAs, which is advantageous for further applications.

scholarly journals Advances in La-Based High-k Dielectrics for MOS Applications

Coatings ◽  
2019 ◽  
Vol 9 (4) ◽  
pp. 217 ◽  
Author(s):  
L. Liu ◽  
W. Tang ◽  
P. Lai
Keyword(s):  
High Performance ◽  
Oxygen Vacancies ◽  
Thin Film Transistor ◽  
Oxide Semiconductor ◽  
Performance Requirements ◽  
Mos Devices ◽  
High K ◽  
Non Volatile Memory ◽  
Boundary States ◽  
Physical And Chemical

This paper reviews the studies on La-based high-k dielectrics for metal-oxide-semiconductor (MOS) applications in recent years. According to the analyses of the physical and chemical characteristics of La2O3, its hygroscopicity and defects (oxygen vacancies, oxygen interstitials, interface states, and grain boundary states) are the main problems for high-performance devices. Reports show that post-deposition treatments (high temperature, laser), nitrogen incorporation and doping by other high-k material are capable of solving these problems. On the other hand, doping La into other high-k oxides can effectively passivate their oxygen vacancies and improve the threshold voltages of relevant MOS devices, thus improving the device performance. Investigations on MOS devices including non-volatile memory, MOS field-effect transistor, thin-film transistor, and novel devices (FinFET and nanowire-based transistor) suggest that La-based high-k dielectrics have high potential to fulfill the high-performance requirements in future MOS applications.

scholarly journals Physical modeling of electrical and dielectric properties of high-k ta2o5 based MOS capacitors on silicon

2014 ◽  
Vol 27 (2) ◽  
pp. 259-273 ◽  
Author(s):  
Nenad Novkovski
Keyword(s):  
Dielectric Properties ◽  
Silicon Oxynitride ◽  
Silicon Substrates ◽  
Leakage Currents ◽  
Mos Capacitors ◽  
Metal Gates ◽  
High K ◽  
Electrical And Dielectric Properties ◽  
High K Dielectric ◽  
Mos Structures

In this paper we present an integral physical model for describing electrical and dielectric properties of MOS structures containing dielectric stack composed of a high-k dielectric (with emphasize on pure and doped Ta2O5) and an interfacial silicon dioxide or silicon oxynitride layer. Based on the model, an equivalent circuit of the structure is proposed. Validity of the model was demonstrated for structures containing different metal gates (Al, Au, Pt, W, TiN, Mo) and different Ta2O5 based high-k dielectrics, grown of bare or nitrided silicon substrates. The model describes very well the I-V characteristics of the considered structures, as well as frequency dependence of the capacitance in accumulation. Stress-induced leakage currents are also effectively analyzed by the use of the model.

High Performance RF FETs Using High-k Dielectrics on Wafer-Scale Quasi-Free-Standing Epitaxial Graphene

2012 ◽  
Vol 717-720 ◽  
pp. 669-674
Author(s):  
Joshua A. Robinson ◽  
Matthew J. Hollander ◽  
Michael LaBella ◽  
Kathleen Trumbull ◽  
Mike Zhu ◽  
...  
Keyword(s):  
Contact Resistance ◽  
High Frequency ◽  
High Performance ◽  
Carrier Transport ◽  
Ohmic Contacts ◽  
Epitaxial Graphene ◽  
Specific Contact Resistance ◽  
Free Standing ◽  
High K ◽  
Specific Contact

We explore the effect of processing on graphene/metal ohmic contact resistance, the integration of high-κ dielectric seeds and overlayers on carrier transport in epitaxial graphene, and directly demonstrate the importance of buffer elimination at the graphene/SiC(0001) interface for high frequency applications. We present a robust method for forming high quality ohmic contacts to graphene, which improves the contact resistance by nearly 6000x compared to untreated metal/graphene interfaces. Optimal specific contact resistance for treated Ti/Au contacts is found to average -7 Ohm-cm2. Additionally, we introduce a novel seeding technique for depositing dielectrics by ALD that utilizes direct deposition of high-κ seed layers and can lead to an increase in Hall mobility up to 70% from as-grown. Finally, we demonstrate that buffer elimination at the graphene/SiC(0001) results in excellent high frequency performance of graphene transistors with fT > 130 GHz at 75 nm gate lengths.

Microstructure of sputter deposited Ni-Sb ohmic contacts on GaAs

1989 ◽  
Vol 47 ◽  
pp. 450-451
Author(s):  
S. Yegnasubramanian ◽  
V.C. Kannan ◽  
R. Dutto ◽  
P.J. Sakach
Keyword(s):  
High Performance ◽  
Ohmic Contacts ◽  
Surface Defects ◽  
Pure Metal ◽  
Device Fabrication ◽  
Native Oxide ◽  
Metal Thin Films ◽  
Recent Developments ◽  
Different Temperatures ◽  
Sputter Deposited

Recent developments in the fabrication of high performance GaAs devices impose crucial requirements of low resistance ohmic contacts with excellent contact properties such as, thermal stability, contact resistivity, contact depth, Schottky barrier height etc. The nature of the interface plays an important role in the stability of the contacts due to problems associated with interdiffusion and compound formation at the interface during device fabrication. Contacts of pure metal thin films on GaAs are not desirable due to the presence of the native oxide and surface defects at the interface. Nickel has been used as a contact metal on GaAs and has been found to be reactive at low temperatures. Formation Of Ni2 GaAs at 200 - 350C is reported and is found to grow epitaxially on (001) and on (111) GaAs, but is shown to be unstable at 450C. This paper reports the investigations carried out to understand the microstructure, nature of the interface and composition of sputter deposited and annealed (at different temperatures) Ni-Sb ohmic contacts on GaAs by TEM. Attempts were made to correlate the electrical properties of the films such as the sheet resistance and contact resistance, with the microstructure. The observations are corroborated by Scanning Auger Microprobe (SAM) investigations.

Sub-20nm Device Voltage-Sensitive SRAM Characterization and Failure Analysis

2018 ◽  
Author(s):  
Seng Nguon Ting ◽  
Hsien-Ching Lo ◽  
Donald Nedeau ◽  
Aaron Sinnott ◽  
Felix Beaudoin
Keyword(s):  
Failure Analysis ◽  
High Performance ◽  
Yield Loss ◽  
Technology Development ◽  
High Density ◽  
High K ◽  
Yield Learning ◽  
Oxide Deposition ◽  
Edge Profile ◽  
High K Dielectric

Abstract With rapid scaling of semiconductor devices, new and more complicated challenges emerge as technology development progresses. In SRAM yield learning vehicles, it is becoming increasingly difficult to differentiate the voltage-sensitive SRAM yield loss from the expected hard bit-cells failures. It can only be accomplished by extensively leveraging yield, layout analysis and fault localization in sub-micron devices. In this paper, we describe the successful debugging of the yield gap observed between the High Density and the High Performance bit-cells. The SRAM yield loss is observed to be strongly modulated by different active sizing between two pull up (PU) bit-cells. Failure analysis focused at the weak point vicinity successfully identified abnormal poly edge profile with systematic High k Dielectric shorts. Tight active space on High Density cells led to limitation of complete trench gap-fill creating void filled with gate material. Thanks to this knowledge, the process was optimized with “Skip Active Atomic Level Oxide Deposition” step improving trench gap-fill margin.

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