Design and Process Issues for Silicon Carbide Power DiMOSFETS

2000 ◽  
Vol 640 ◽  
Author(s):  
Sei-Hyung Ryu ◽  
Anant K. Agarwal ◽  
Nelson S. Saks ◽  
Mrinal K. Das ◽  
Lori A. Lipkin ◽  
...  
Keyword(s):  
Silicon Carbide ◽  
Drain Current ◽  
Gate Oxide ◽  
Channel Structure ◽  
Channel Mobility ◽  
Power Mosfets ◽  
Buried Channel ◽  
P Type ◽  
Very High ◽  
Effective Channel

ABSTRACTThis paper discusses the design and process issues of high voltage power DiMOSFETs (Double implanted MOSFETs) in 4H-silicon carbide (SiC). Since Critical Field (EC) in 4H-SiC is very high (10X higher than that of a Si), special care is needed to protect the gate oxide. 2D device simulation tool was used to determine the optimal JFET gap, which provides adequate gate oxide protection as well as a reasonable JFET resistance. The other issue in 4H-SiC DiMOSFETs is extremely low effective channel mobility (μeff) in the implanted p-well regions. NO anneal of the gate oxide and buried channel structure are used for increasing μeff. NO anneal, which was reported to be very effective in increasing the μeff of SiC MOSFETS in p-type epilayers, did not produce reasonable μeff of SiC MOSFETs in the implanted p-well. Buried channel (BC) structure with 2.7×1012 cm−2 charge in the channel showed high μeff utilizing bulk buried channel, but resulted in a normally-on device. However, it was shown that by controlling the charge in the BC layer, a normally off device with high μeff can be produced. A 3.3 mm × 3.3 mm DiMOSFET with BC structure showed a drain current of 10 A, which is the highest current reported in SiC power MOSFETs to date, at a forward drop of 4.4 V with a gate bias of only 2.5 V.

Impact of Channel Mobility Improvement Using Boron Diffusion on Different Power MOSFETs Voltage Classes

2017 ◽  
Vol 897 ◽  
pp. 537-540
Author(s):  
Victor Soler ◽  
Maria Cabello ◽  
Maxime Berthou ◽  
Josep Montserrat ◽  
José Rebollo ◽  
...  
Keyword(s):  
Gate Oxide ◽  
Pin Diode ◽  
Boron Diffusion ◽  
Oxide Formation ◽  
Interface Quality ◽  
Channel Mobility ◽  
Power Mosfets ◽  
The Impact ◽  
Effective Channel ◽  
Drift Layer

SiC planar VDMOS of three voltages ratings (1.7kV, 3.3kV and 4.5kV) have been fabricated using a Boron diffusion process into the thermal gate oxide for improving the SiO2/SiC interface quality. Experimental results show a remarkable increase of the effective channel mobility which increases the device current capability, especially at room temperatures. At high temperatures, the impact of the Boron treatment is lower since the major contribution of the drift layer to the on-resistance. In addition, the intrinsic body diode characteristics approximate to that of an ideal PiN diode, and the blocking capability is not compromised by the use of Boron for the gate oxide formation.

The Characteristics of MOSFETs Fabricated on the Trench Sidewalls of Various Faces Using 4H-SiC (11-20) Substrates

2006 ◽  
Vol 527-529 ◽  
pp. 1297-1300
Author(s):  
Hiroyuki Fujisawa ◽  
Takashi Tsuji ◽  
Masaharu Nishiura
Keyword(s):  
Drain Current ◽  
Gate Oxide ◽  
Channel Mobility ◽  
Effective Channel

This paper reports the channel mobilities of MOSFETs formed on the trench sidewalls with different crystal faces including (0001), (000-1), (1-100) and (0-33-8) using 4H-SiC (11-20) substrates. Deposited poly-Si was oxidized in wet ambient to form the gate oxide, and annealed in N2O (10%) ambient. The order of drain current of trench sidewall MOSFETs was (0-33-8) > (1-100) > (000-1) = (0001). We could gain comparatively high channel mobility on the (0-33-8) face. The maximum effective channel mobility (μeff) was 35cm2/Vs, and μeff at 2.5MV/cm was 29 cm2/Vs on the (0-33-8) face.

Elevated Temperature Operation of 4H-SiC Nanoribbon Field Effect Transistors

2015 ◽  
Vol 15 (10) ◽  
pp. 7551-7554 ◽  
Author(s):  
Min Seok Kang ◽  
Susanna Yu ◽  
Sang Mo Koo
Keyword(s):  
Elevated Temperature ◽  
Plasma Etching ◽  
Field Effect ◽  
Heat Dissipation ◽  
Field Effect Transistors ◽  
Drain Current ◽  
Top Down ◽  
Channel Mobility ◽  
Channel Thickness ◽  
Effective Channel

We fabricated 4H-SiC nanoribbon field effect transistors (FETs) of various channel thickness (tch) of 100∼500 nm by a “top–down” approach, using a lithography and plasma etching process. We studied the dependence of the device transfer characteristics on the channel geometry. This demonstrated that fabricated SiC nanoribbon FETs with a tch of 100 nm show normally-on characteristics, and have a threshold voltage of −12 V, and a maximum transconductance value of 8.8 mS, which shows improved drain current degradation of the SiC nanoribbon FETs with tch =100 nm at elevated temperature. This can be attributed to the improved heat dissipation, enhanced channel mobility, and together with widening of effective channel thickness depletion induced.

Fabrication of 4H-SiC p-Channel MOSFET with High Channel Mobility

2006 ◽  
Vol 527-529 ◽  
pp. 1301-1304
Author(s):  
Mitsuo Okamoto ◽  
Mieko Tanaka ◽  
Tsutomu Yatsuo ◽  
Kenji Fukuda
Keyword(s):  
Valence Band ◽  
Oxidation Process ◽  
Gate Oxide ◽  
Interface States ◽  
Wet Oxidation ◽  
Mos Capacitors ◽  
Channel Mobility ◽  
Dry Oxidation ◽  
Low Threshold ◽  
P Type

We have fabricated inversion-type p-channel MOSFETs on 4H-SiC substrates. In this paper, influences of gate oxidation process on the properties of p-channel MOSFETs were investigated. The gate oxide was formed under these three conditions: (i) dry oxidation, (ii) dry oxidation following wet re-oxidation, and (iii) wet oxidation. The C-V measurements of p-type 4H-SiC MOS capacitors revealed that wet oxidation process reduced the interface states near the valence band. The p-channel MOSFET with low interface states near the valence band indicated low threshold voltage (Vth), high field effect channel mobility (μFE) and low subthreshold swing (S). We obtained 4H-SiC p-channel MOSFET with high μFE of 15.6cm2/Vs by using wet oxidation as gate oxidation process.

Effect of Negative Gate Bias on Single Pulse Avalanche Ruggedness of 1.2 kV Silicon Carbide MOSFETs

2018 ◽  
Vol 924 ◽  
pp. 735-738 ◽  
Author(s):  
Selamnesh Nida ◽  
Thomas Ziemann ◽  
Bhagyalakshmi Kakarla ◽  
Ulrike Grossner
Keyword(s):  
Silicon Carbide ◽  
Single Pulse ◽  
Gate Oxide ◽  
Gate Bias ◽  
Power Mosfets ◽  
Self Heating ◽  
Significant Difference ◽  
Oxide Defects ◽  
Voltage Spike ◽  
Avalanche Generation

When power MOSFETs experience a voltage spike initiating avalanche generation, a large amount of power is dissipated at the device junction. This leads to self-heating and lowers the threshold voltage. Some sources indicate that unintended opening of the channel creates a positive feedback, thereby increasing heat generation and leading to thermal runaway. Therefore, keeping MOSFETs off by applying a negative gate bias should improve avalanche ruggedness. In this report, this claim is investigated by comparing single pulse avalanche ruggedness of commercial 1.2 kV, 80 mΩ planar and trench MOSFETs at -10 V and 0 V off-state gate bias. Both planar and trench devices show a small increase in their breakdown voltage with negative gate bias. However, there is no significant difference in avalanche withstanding energy. Even in investigated trench gate devices where the gate oxide is susceptible to interface as well as oxide defects, keeping the gate voltage at VGS = -10 V did not result in improvements in ruggedness.

Improved Evaluation Method for Channel Mobility in SiC Trench MOSFETs

2015 ◽  
Vol 821-823 ◽  
pp. 757-760 ◽  
Author(s):  
Katsuhiro Kutsuki ◽  
Sachiko Kawaji ◽  
Yukihiko Watanabe ◽  
Shinichiro Miyahara ◽  
Jun Saito
Keyword(s):  
Evaluation Method ◽  
Drain Current ◽  
Interface State ◽  
State Density ◽  
Effective Field ◽  
Channel Mobility ◽  
Definition Of ◽  
Effective Channel ◽  
Dominant Influence ◽  
The Ideal

We proposed an improved method for evaluating the effective channel mobility (μeff), involving an appropriate definition of the threshold voltage (Vth) based on the ideal gate bias voltage – drain current (VG-ID) characteristics. Using this method, the dependence of μeff on the effective field (Eeff) could be evaluated even for SiC trench MOSFETs with large interface state density (Dit) values. The dominant influence on μeff in the low Eeff region was found to be Coulomb scattering caused by interface states at the SiC/SiO2 interfaces.

Effective Channel Mobility in Epitaxial and Implanted 4H-SiC Lateral MOSFETs

2008 ◽  
Vol 1069 ◽  
Author(s):  
Sarah Kay Haney ◽  
Sei-Hyung Ryu ◽  
Sarit Dhar ◽  
Anant Agarwal ◽  
Mark Johnson
Keyword(s):  
Ion Implantation ◽  
Inversion Layer ◽  
Negative Effects ◽  
Channel Mobility ◽  
Epitaxial Regrowth ◽  
Threshold Voltages ◽  
P Type ◽  
Effective Channel

ABSTRACTIn this paper, we investigate the effective inversion layer mobility of lateral 4H-SiC MOSFETs. Initially, lateral n-channel MOSFETs were fabricated to determine the effect of p-type epi-regrowth on a highly doped p-well surface. The negative effects of the high p-well doping are still seen with 1500 Å p-type regrowth, while growing 0.5 um or more appears to be sufficient to grow out of the damaged area. A second experiment was performed to examine the effects of doping during epitaxial regrowth versus using ion implantation after regrowth. Comparable mobilities and threshold voltages were observed for equivalent epitaxial and implanted doping concentrations.

3C-SiC MOSFET with High Channel Mobility and CVD Gate Oxide

2011 ◽  
Vol 679-680 ◽  
pp. 645-648 ◽  
Author(s):  
Motoki Kobayashi ◽  
Hidetsugu Uchida ◽  
Akiyuki Minami ◽  
Toyokazu Sakata ◽  
Romain Esteve ◽  
...  
Keyword(s):  
Titanium Nitride ◽  
High Performance ◽  
Room Temperature ◽  
Drain Current ◽  
Gate Oxide ◽  
Channel Mobility ◽  
Thermally Grown Oxides ◽  
Metal Gates ◽  
Blocking Voltage ◽  
Gate Oxide Integrity

3C-SiC MOSFET with 200 cm2/Vs channel mobility was fabricated. High performance device processes were adopted, including room temperature implantation with resist mask, polysilicon-metal gates, aluminium interconnects with titanium and titanium nitride and a specially developed activation anneal at 1600°C in Ar to get a smooth 3C-SiC surface and hence the expected high channel mobility. CVD deposited oxide with post oxidation annealing was investigated to reduce unwanted oxide charges and hence to get a better gate oxide integrity compared to thermally grown oxides. 3C-SiC MOSFETs with 600 V blocking voltage and 10 A drain current were fabricated using the improved processes described above. The MOSFETs assembled with TO-220 PKG indicated specific on-resistances of 5 to 7 mΩcm2.

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