Via Cleaning Technology for Post Etch Residues

2005 ◽  
Vol 103-104 ◽  
pp. 357-360
Author(s):  
B.G. Sharma ◽  
Chris Prindle
Keyword(s):  
Semiconductor Industry ◽  
Dielectric Materials ◽  
Copper Interconnects ◽  
Limiting Factor ◽  
Device Performance ◽  
Semiconductor Technology ◽  
Widespread Acceptance ◽  
Cleaning Technology ◽  
Rc Delay ◽  
Low K

Interconnect RC delay is the limiting factor for device performance in submicron semiconductor technology. Copper and low-k dielectric materials can reduce this delay and have gained widespread acceptance in the semiconductor industry. The presence of copper interconnects provides unprecedented challenges for via cleaning technology and requires the development of novel process chemistries for improved device capability.

Overview Of Process Integration Issues For Low K Dielectrics

1998 ◽  
Vol 511 ◽  
Author(s):  
R. H. Havemann ◽  
M. K. Jain ◽  
R. S. List ◽  
A. R. Ralston ◽  
W-Y. Shih ◽  
...  
Keyword(s):  
Large Scale ◽  
Process Integration ◽  
Functional Integration ◽  
Dielectric Materials ◽  
Limiting Factor ◽  
Large Scale Integration ◽  
On Chip ◽  
Scale Integration ◽  
Rc Delay ◽  
Low K

ABSTRACTThe era of silicon Ultra-Large-Scale-Integration (ULSI) has spurred an everincreasing level of functional integration on-chip, driving a need for greater circuit density and higher performance. While traditional transistor scaling has thus far met this challenge, interconnect scaling has become the performance-limiting factor for new designs. Both interconnect resistance and capacitance play key roles in overall performance, but modeling simulations have highlighted the importance of reducing parasitic capacitance to manage crosstalk, power dissipation and RC delay. New dielectric materials with lower permittivity (k) are needed to meet this challenge. This paper summarizes the process integration and reliability issues associated with the use of novel low k materials in multilevel interconnects.

The Study of Fluorinated Amorphous Carbon as Low-K Dielectric Material and its Interface with Copper Metallization

1999 ◽  
Vol 565 ◽  
Author(s):  
N. Ariel ◽  
M. Eizenberg ◽  
E. Y. Tzou
Keyword(s):  
Amorphous Carbon ◽  
Nuclear Reactions ◽  
Dielectric Material ◽  
Copper Metallization ◽  
Limiting Factor ◽  
Adhesion Promoter ◽  
Adhesion Promotion ◽  
High Resolution Tem ◽  
Rc Delay ◽  
Low K

AbstractIn order to achieve better performance of devices, the interconnects RC delay time, the limiting factor of the device speed today, must be reduced. This calls for a new interconnect stack: lower resistivity Copper and low k materials (k<3) as dielectrics.Fluorinated amorphous carbon (a-F:C) prepared by HDP- CVD is an attractive candidate as a low-k material. In this work we have studied the film, its stability and its interface with Copper metallization. The high density plasma CVD process resulted in a film which contains C and F at a ratio of 1:0.6 as determined by Nuclear Reactions Analysis. XPS analysis of the Cls transition indicated four types of bonds: C-C, C-CF, CF, and CF2. X-ray diffraction as well as high resolution TEM analyses proved that the film was amorphous at least up to 500°C anneal. For various applications, the advantage of adding a thin bi-layer of a-SiC/SiOx for adhesion promotion purposes was demonstrated. In addition, the interface of a-F:C and the adhesion promoter layer with Ta, TaN and Cu was studied. No interdiffusion was observed by SIMS after 400°C annealing. 500°C annealing caused F outdiffusion from the film and Cu diffusion into the adhesion promoter layer.

Effect of Complex Agent on Copper Dissolution in Alkaline Slurry for Chemical Mechanical Planarization

2012 ◽  
Vol 455-456 ◽  
pp. 1145-1148
Author(s):  
Yan Gang He ◽  
Jia Xi Wang ◽  
Xiao Wei Gan ◽  
Wei Juan Li ◽  
Yu Ling Liu
Keyword(s):  
Surface Roughness ◽  
Removal Rate ◽  
Chemical Mechanical Planarization ◽  
Dielectric Materials ◽  
Mechanism Analysis ◽  
Copper Dissolution ◽  
Complex Agent ◽  
High Removal Rate ◽  
Rc Delay ◽  
Low K

With the microelectronic technology node moves down to 45 nm and beyond, and to reduce the RC delay time, low-k dielectric materials have been used to replace regular dielectric materials. Therefore, the down force of chemical mechanical planarization (CMP) needs to decrease based on the characteristics of low-k materials: low mechanical strength. In this study, the effect of new complex agent on copper dissolution in alkaline slurry for CMP was investigated. Based on the reaction mechanism analysis of Cu in alkaline slurry in CMP, the performance of Cu removal rate and surface roughness condition were discussed. It has been confirmed that Cu1 slurry demonstrates a relatively high removal rate with low down force. And also, by utilizing the Cu1 slurry, good result of Cu surface roughness were obtained.

The Study of Fluorinated Amorphous Carbon as Low-K Dielectric Material and its Interface with Copper Metallization

1999 ◽  
Vol 564 ◽  
Author(s):  
N. Ariel ◽  
M. Eizenberg ◽  
E. Y. Tzou
Keyword(s):  
Amorphous Carbon ◽  
Nuclear Reactions ◽  
Dielectric Material ◽  
Copper Metallization ◽  
Limiting Factor ◽  
Adhesion Promoter ◽  
Adhesion Promotion ◽  
High Resolution Tem ◽  
Rc Delay ◽  
Low K

AbstractIn order to achieve better performance of devices, the interconnects RC delay time, the limiting factor of the device speed today, must be reduced. This calls for a new interconnect stack: lower resistivity Copper and low k materials (k<3) as dielectrics.Fluorinated amorphous carbon (a-F:C) prepared by HDP- CVD is an attractive candidate as a low-k material. In this work we have studied the film, its stability and its interface with Copper metallization. The high density plasma CVD process resulted in a film which contains C and F at a ratio of 1:0.6 as determined by Nuclear Reactions Analysis. XPS analysis of the C Is transition indicated four types of bonds: C-C, C-CF, CF, and CF2. X-ray diffraction as well as high resolution TEM analyses proved that the film was amorphous at least up to 500°C anneal. For various applications, the advantage of adding a thin bi-layer of a-SiC/SiOx for adhesion promotion purposes was demonstrated. In addition, the interface of a-F:C and the adhesion promoter layer with Ta, TaN and Cu was studied. No interdiffusion was observed by SIMS after 400°C annealing. 500°C annealing caused F outdiffusion from the film and Cu diffusion into the adhesion promoter layer.

Nondestructive Defect Imaging through Image Intensity Analysis

2007 ◽  
Author(s):  
J. Demarest ◽  
D. Bearup ◽  
A. Dalton ◽  
L. Hahn ◽  
B. Redder ◽  
...  
Keyword(s):  
Electron Beam ◽  
Dielectric Material ◽  
Natural Extension ◽  
Dielectric Materials ◽  
Intensity Analysis ◽  
Semiconductor Technology ◽  
Pixel Location ◽  
Imaging Mode ◽  
Defect Imaging ◽  
Low K

Abstract The continually shrinking dimensions of today’s semiconductor technology occasionally allow for novel approaches in imaging defects. It has become desirable to image subsurface voids prior to cross sectioning and some efforts have been made to address this need including the construction of specialized instrumentation [1]. The thickness of the metallization levels at the 65 nm technology node and smaller now allow for the use of the electron beam in a scanning electron microscope (SEM) as a material sensor. At high accelerating voltages (between 20-30 kV) in backscatter imaging mode the numerical gray level values at each pixel location can correlate to the amount of material directly under the electron beam at that location. This is particularly evident when dealing with defined geometries and material sets offering high contrast changes between materials such as those found in semiconductor technology like copper (Cu) metal and conventional dielectric materials. As a result, subsurface voids can be mapped to a reasonable representation prior to cross sectioning and precise pinpointing of the defect location in test structures can occur. This paper discusses this methodology on 65 nm technology with Cu metal lines in a low-k dielectric material for a two level metal test structure. To some extent this work represents a natural extension of a paper presented previously by the author [2].

Silsesquioxane-based Photopatternable Porous Low-k Dielectric Materials

2010 ◽  
Vol 1249 ◽  
Author(s):  
Alshakim Nelson ◽  
Jitendra S Rathore ◽  
Blake Davis ◽  
Phillip Brock ◽  
Ratnam Sooriyakumaran ◽  
...  
Keyword(s):  
Semiconductor Manufacturing ◽  
Extreme Ultraviolet ◽  
Dielectric Material ◽  
Semiconductor Industry ◽  
Dielectric Materials ◽  
Patterned Structures ◽  
Sacrificial Layers ◽  
Wafer Processing ◽  
Low K ◽  
Processing Steps

AbstractThe future resolution requirements for the semiconductor industry demand advanced lithographic techniques, such as immersion and extreme ultraviolet (EUV) technologies, which will increase the cost of microelectronics manufacturing. Currently, low-k dielectric materials, which are used as insulating layers between the copper wiring, are indirectly patterned using a set of sacrificial layers and etch processes. The sacrificial layers include a photoresist polymer that must first be imaged prior to transferring the pattern to the underlying layers, including the dielectric layer. In order to reduce the number of processing steps required for semiconductor manufacturing, we have developed a novel photo-patternable low-k dielectric material that (1) eliminates the need for sacrificial layers and (2) reduces the number of wafer processing steps. Silsesquioxane copolymers that undergo acid-catalyzed crosslinking when exposed to 193nm wavelength were synthesized. In addition to the direct photo-patternability, the patterned structures are suitable as a dielectric material with a dielectric constant as low as 2.4, and an appreciable elastic modulus (E > 4.0 GPa). These photo-patternable low-k materials represent a ‘greener' approach to semiconductor manufacturing which has the ability to reduce cost, waste materials, and energy consumption.

Application of AFP Nanoprobing Light-Induced Photovoltaic Current in the Failure Analysis

2017 ◽  
Author(s):  
C.Q. Chen ◽  
P.T. Ng ◽  
G.B. Ang ◽  
Francis Rivai ◽  
S.L. Ting ◽  
...  
Keyword(s):  
Image Analysis ◽  
Failure Analysis ◽  
Photovoltaic Effect ◽  
Electrical Characterization ◽  
Fault Isolation ◽  
Device Performance ◽  
Semiconductor Technology ◽  
Current Image ◽  
Scaling Down ◽  
Detailed Circuit

Abstract As semiconductor technology keeps scaling down, failure analysis and device characterizations become more and more challenging. Global fault isolation without detailed circuit information comprises the majority of foundry EFA cases. Certain suspected areas can be isolated, but further narrow-down of transistor and device performance is very important with regards to process monitoring and failure analysis. A nanoprobing methodology is widely applied in advanced failure analysis, especially during device level electrical characterization. It is useful to verify device performance and to prove the problematic structure electrically. But sometimes the EFA spot coverage is too big to do nanoprobing analysis. Then further narrow-down is quite critical to identify the suspected structure before nanoprobing is employed. That means there is a gap between global fault isolation and localized device analysis. Under these kinds of situation, PVC and AFP current image are offen options to identify the suspected structure, but they still have their limitation for many soft defect or marginal fails. As in this case, PVC and AFP current image failed to identify the defect in the spot range. To overcome the shortage of PVC and AFP current image analysis, laser was innovatively applied in our current image analysis in this paper. As is known to all, proper wavelength laser can induce the photovoltaic effect in the device. The photovoltaic effect induced photo current can bring with it some information of the device. If this kind of information was properly interpreted, it can give us some clue of the device performance.

Failure Modes, Reliability Analysis and Case Studies on the Integration of Copper and Low-K Technology

2004 ◽  
Author(s):  
Huixian Wu ◽  
James Cargo ◽  
Huixian Wu ◽  
Marvin White
Keyword(s):  
Failure Analysis ◽  
Case Studies ◽  
Cross Section ◽  
Focused Ion Beam ◽  
Failure Modes ◽  
Ion Beam ◽  
Copper Interconnects ◽  
Wet Chemical ◽  
Low K ◽  
Section Analysis

Abstract The integration of copper interconnects and low-K dielectrics will present novel failure modes and reliability issues to failure analysts. This paper discusses failure modes related to Cu/low-K technology. Here, physical failure analysis (FA) techniques including deprocessing and cross-section analysis have been developed. The deprocessing techniques include wet chemical etching, reactive ion etching, chemical mechanical polishing and a combination of these techniques. Case studies on different failure modes related to Cu/low k technology are discussed: copper voiding, copper extrusion; electromigration stress failure; dielectric cracks; delamination-interface adhesion; and FA on circuit-under-pad. For the cross-section analysis of copper/low-K samples, focused ion beam techniques have been developed. Scanning electron microscopy, EDX, and TEM analytical analysis have been used for failure analysis for Cu/low-K technology. Various failure modes and reliability issues have also been addressed.

Studies of the Coefficient of Thermal Expansion of Low-k ILD Materials by X-Ray Reflectivity

2006 ◽  
Vol 914 ◽  
Author(s):  
George Andrew Antonelli ◽  
Tran M. Phung ◽  
Clay D. Mortensen ◽  
David Johnson ◽  
Michael D. Goodner ◽  
...  
Keyword(s):  
Thin Films ◽  
Thermal Expansion ◽  
Coefficient Of Thermal Expansion ◽  
Chemical Vapor ◽  
Dielectric Materials ◽  
Free Standing ◽  
Dielectric Thin Films ◽  
X Ray ◽  
Chemical Vapor Deposited ◽  
Low K

AbstractThe electrical and mechanical properties of low-k dielectric materials have received a great deal of attention in recent years; however, measurements of thermal properties such as the coefficient of thermal expansion remain minimal. This absence of data is due in part to the limited number of experimental techniques capable of measuring this parameter. Even when data does exist, it has generally not been collected on samples of a thickness relevant to current and future integrated processes. We present a procedure for using x-ray reflectivity to measure the coefficient of thermal expansion of sub-micron dielectric thin films. In particular, we elucidate the thin film mechanics required to extract this parameter for a supported film as opposed to a free-standing film. Results of measurements for a series of plasma-enhanced chemical vapor deposited and spin-on low-k dielectric thin films will be provided and compared.

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