Application of AFP Nanoprobing Light-Induced Photovoltaic Current in the Failure Analysis

2017 ◽  
Author(s):  
C.Q. Chen ◽  
P.T. Ng ◽  
G.B. Ang ◽  
Francis Rivai ◽  
S.L. Ting ◽  
...  
Keyword(s):  
Image Analysis ◽  
Failure Analysis ◽  
Photovoltaic Effect ◽  
Electrical Characterization ◽  
Fault Isolation ◽  
Device Performance ◽  
Semiconductor Technology ◽  
Current Image ◽  
Scaling Down ◽  
Detailed Circuit

Abstract As semiconductor technology keeps scaling down, failure analysis and device characterizations become more and more challenging. Global fault isolation without detailed circuit information comprises the majority of foundry EFA cases. Certain suspected areas can be isolated, but further narrow-down of transistor and device performance is very important with regards to process monitoring and failure analysis. A nanoprobing methodology is widely applied in advanced failure analysis, especially during device level electrical characterization. It is useful to verify device performance and to prove the problematic structure electrically. But sometimes the EFA spot coverage is too big to do nanoprobing analysis. Then further narrow-down is quite critical to identify the suspected structure before nanoprobing is employed. That means there is a gap between global fault isolation and localized device analysis. Under these kinds of situation, PVC and AFP current image are offen options to identify the suspected structure, but they still have their limitation for many soft defect or marginal fails. As in this case, PVC and AFP current image failed to identify the defect in the spot range. To overcome the shortage of PVC and AFP current image analysis, laser was innovatively applied in our current image analysis in this paper. As is known to all, proper wavelength laser can induce the photovoltaic effect in the device. The photovoltaic effect induced photo current can bring with it some information of the device. If this kind of information was properly interpreted, it can give us some clue of the device performance.

Electrical and Nanoprobing Analysis on the Implantation-Related Invisible Defect

2016 ◽  
Author(s):  
C.Q. Chen ◽  
P.T. Ng ◽  
G.B. Ang ◽  
Francis Rivai ◽  
A.C.T. Quah ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Process Analysis ◽  
Electrical Characterization ◽  
Fault Isolation ◽  
Device Performance ◽  
Device Physics ◽  
Theory Analysis ◽  
Process Step ◽  
Advantages And Disadvantages ◽  
Detailed Circuit

Abstract As semiconductor technology keeps scaling down, failure analysis and device characterizations become more and more challenging. Global fault isolation without detailed circuit information comprises the majority of foundry EFA cases. Certain suspected areas can be isolated, but further narrow-down of transistor and device performance is very important with regards to process monitoring and failure analysis. A nanoprobing methodology is widely applied in advanced failure analysis, especially during device level electrical characterization. It is useful to verify device performance and to prove the problematic structure electrically, especially for implantation related problems [1] [2]. Implantation related defects, or invisible defects, are the most challenging defect types for the application of fault isolation in all of the failure analysis jobs. The key challenge for these kinds of analyses is to make the defect visible. Sometimes, it is difficult or even impossible to visualize the defective point. Then, sufficient electrical evidence and theory analysis are important to bring the issue to resolution. For these kinds of analyses, a nanoprobing system is a necessary tool to conduct the detailed analysis. Combined with the device physics and electrical theory analysis, nanoprobing can bring out the perfect failure mechanism and problematic process step. There are two popular nanoprobing systems in our lab, one is SEM based and the other is AFM based. Both systems have their advantages and disadvantages in the electrical characterization and fault isolation field. In this paper, an implantation related issue was analyzed. Gross leakage was observed on the failed units as compared with good units. Global fault isolation, TIVA and EMMI failed to find the exclusive hotspot. With the GDS and process analysis, the nanoprobing was employed to the performance check on some of the suspected structures. Finally, the defective location was successfully isolated by nanoprobing. Combined with device physics and electrical analysis, the problematic process was successfully isolated.

Failure Analysis for Inter-Level Short in Nanometer Semiconductor Technologies

2018 ◽  
Author(s):  
Zhigang Song
Keyword(s):  
Failure Analysis ◽  
Failure Mechanism ◽  
Case Studies ◽  
Process Variation ◽  
Failure Mechanisms ◽  
Semiconductor Technology ◽  
New Materials ◽  
Analysis Methodology ◽  
Scaling Down ◽  
Nanometer Regime

Abstract As semiconductor technology keeps scaling down, plus new structures of transistor and new materials introduction, not only are new failure mechanisms introduced, but also old classic failure mechanisms get evolved. The obvious example of failure mechanism evolution is short defect. In the previous technologies, although short defects can happen in different layers and appear in different forms, they always happens at intra-level. As semiconductor technology advanced into nanometer regime, short defect no longer only happened in intra-level, but also more and more often happened in interlevel. Failure analysis on the inter-level short defects is much more challenging because they are usually due to interaction of two processes, such as process variation in two process steps at the same location, and often hide in the bottom of tapered and dense patterns. The conventional PFA (Physical Failure Analysis) methodology often misses discovering the defect and then the defect will be removed by subsequent polishing. This paper has demonstrated some methods to tackle the challenges with three case studies of such inter-level short defects in nanometer semiconductor technologies.

Static Fault Isolation on the Functional Failure Analysis

2014 ◽  
Author(s):  
C.Q. Chen ◽  
Z.H. Mai ◽  
G.B. Ang ◽  
B.H. Liu ◽  
P.T. Ng ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Process Analysis ◽  
Photon Emission ◽  
Fault Isolation ◽  
Induced Current ◽  
Ic Design ◽  
Functional Failure ◽  
Voltage Change ◽  
Dc Bias ◽  
Scaling Down

Abstract As the technology keeps scaling down and IC design becomes more and more complex, failure analysis becomes much more challenging, especially for static fault isolation. For semiconductor foundry FA, it will become even more challenging due to lack of enough information. Static fault isolation is the major global fault isolation methodology in foundry FA and it is difficult to access and trigger the failing signal detected by scan and BIST test, which is widely applied in modern IC design. Because, in most of the time, the normal two pin bias (Vdd and Vss) can only get the comparable IV result between bad unit and the reference unit for function related fail. There are two possibilities from reverse engineering perspective. Firstly, the defect location may not be accessed by the DC bias. Secondly, even if the defect can be accessed, but the defect induced current or voltage change is too small to be differentiated from the overall signal. So it will be concealed in the overall current. However, it is still possible for us to do global fault isolation for the second situation. In this paper, a unit with Iddoff failure was analyzed. Although, no significant IV difference was observed between failed and reference units, a distinct Photon Emission (EMMI) spot was successfully observed in the failed unit. Layout analysis and process analysis on this EMMI spot further confirmed the reality of the emission spot.

Fault Isolation Techniques and Studies on Low Resistance Gross Short Failures

2012 ◽  
Author(s):  
P.K. Tan ◽  
Z.H. Mai ◽  
W.Y. Lee ◽  
Y.Z. Ma ◽  
R. He ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Semiconductor Devices ◽  
Fault Isolation ◽  
Nanoscale Devices ◽  
Nanometer Range ◽  
Low Resistance ◽  
Isolation Techniques ◽  
Different Types ◽  
Scaling Down

Abstract With the scaling down of semiconductor devices to nanometer range, fault isolation and physical failure analysis (PFA) have become more challenging. In this paper, different types of fault isolation techniques to identify gross short failures in nanoscale devices are discussed. The proposed cut/deprocess and microprobe/bench technique is an economical and simple way of identifying low resistance gross short failures.

Failure Analysis of Stacked-Chip Scale Package

2000 ◽  
Author(s):  
Christopher C. Flores
Keyword(s):  
Failure Analysis ◽  
Electrical Characterization ◽  
Adhesive Layer ◽  
Fault Isolation ◽  
Packaging Technology ◽  
Molding Compound ◽  
Chip Scale Package ◽  
Glass Fillers ◽  
Test Failure ◽  
Better Than

Abstract Stacked-chip scale package (S-CSP) is a new packaging technology introduced in the memory components market to effect chip miniaturization, a challenging trend in semiconductor assembly. The package is built by molding two stacked dice (Flash and SRAM) on bismaleimide triazine (BT) substrate. As this novel packaging technology offers solution to the challenge, it also poses complexity in the field of failure analysis in cases that the bottom die is the interest. Deprocessing these stacked dice while maintaining the functionality of the bottom die will be explained in detail. Prior the conduct of failure analysis (FA) and fault isolation (FI), deprocessing the failing unit containing only one die normally consists of chemical decapsulation. S-CSP sample preparation also adheres to this treatment in case the top die is the aim for analysis. On the other hand, if the concern shifts to the bottom die, sequential techniques involving precision polishing to die-to-die adhesive layer, chemical etching of adhesive and residual molding compound, and rebonding the bottom die on ceramic interposer, are employed. With the rebonded S-CSP bottom die, fault isolation could be performed further. This paper will also feature the mechanism behind the blown-up failure, a power test failure in memory devices, encountered during the package development when two types of die-to-die adhesives were selected and used. Consistent with the results of electrical characterization suggesting that S-CSP bottom die as the failing die, passivation damage is uncovered on the bottom die upon separation of the stacked dice. Material comparison points out that the hard, angular glass fillers of the die-to-die adhesive induce the damage. Polymer-filled adhesive performs better than the glass-filled adhesive as indicated by the results of the package characterization. Generally, this case exemplifies a packaging material-related failure. Moreover, the paper could serve as a reference material in the event that feasibility of packaging non-memory components in S-CSP is to be evaluated. The developed methodology of recovering the S-CSP bottom die would be a keystone in proacting for its FA readiness.

A New Failure Analysis Flow of Gate Oxide Integrity Failure in Wafer Fabrication

2009 ◽  
Author(s):  
Hua Younan ◽  
Chu Susan ◽  
Gui Dong ◽  
Mo Zhiqiang ◽  
Xing Zhenxiang ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Gate Dielectric ◽  
Dielectric Breakdown ◽  
Defect Density ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Fault Isolation ◽  
Wafer Fabrication ◽  
Root Cause ◽  
Gate Oxide Integrity

Abstract As device feature size continues to shrink, the reducing gate oxide thickness puts more stringent requirements on gate dielectric quality in terms of defect density and contamination concentration. As a result, analyzing gate oxide integrity and dielectric breakdown failures during wafer fabrication becomes more difficult. Using a traditional FA flow and methods some defects were observed after electrical fault isolation using emission microscopic tools such as EMMI and TIVA. Even with some success with conventional FA the root cause was unclear. In this paper, we will propose an analysis flow for GOI failures to improve FA’s success rate. In this new proposed flow both a chemical method, Wright Etch, and SIMS analysis techniques are employed to identify root cause of the GOI failures after EFA fault isolation. In general, the shape of the defect might provide information as to the root cause of the GOI failure, whether related to PID or contamination. However, Wright Etch results are inadequate to answer the questions of whether the failure is caused by contamination or not. If there is a contaminate another technique is required to determine what the contaminant is and where it comes from. If the failure is confirmed to be due to contamination, SIMS is used to further determine the contamination source at the ppm-ppb level. In this paper, a real case of GOI failure will be discussed and presented. Using the new failure analysis flow, the root cause was identified to be iron contamination introduced from a worn out part made of stainless steel.

Electrical Characterization of Different Failure Modes in Sub-100 nm Devices Using Nanoprobing Technique

2009 ◽  
Author(s):  
E. Hendarto ◽  
S.L. Toh ◽  
J. Sudijono ◽  
P.K. Tan ◽  
H. Tan ◽  
...  
Keyword(s):  
Electron Microscope ◽  
Focused Ion Beam ◽  
Failure Modes ◽  
Ion Beam ◽  
Electrical Characterization ◽  
Nickel Silicide ◽  
Fault Isolation ◽  
Technology Nodes ◽  
Scanning Electron

Abstract The scanning electron microscope (SEM) based nanoprobing technique has established itself as an indispensable failure analysis (FA) technique as technology nodes continue to shrink according to Moore's Law. Although it has its share of disadvantages, SEM-based nanoprobing is often preferred because of its advantages over other FA techniques such as focused ion beam in fault isolation. This paper presents the effectiveness of the nanoprobing technique in isolating nanoscale defects in three different cases in sub-100 nm devices: soft-fail defect caused by asymmetrical nickel silicide (NiSi) formation, hard-fail defect caused by abnormal NiSi formation leading to contact-poly short, and isolation of resistive contact in a large electrical test structure. Results suggest that the SEM based nanoprobing technique is particularly useful in identifying causes of soft-fails and plays a very important role in investigating the cause of hard-fails and improving device yield.

The Electrical Characterization and Physical Failure Analysis for Transistor Gate Leakage

2006 ◽  
Author(s):  
Tsung-Te Li ◽  
Chao-Chi Wu ◽  
Jung-Hsiang Chuang ◽  
Jon C. Lee
Keyword(s):  
Failure Analysis ◽  
Electrical Characterization ◽  
Physical Analysis ◽  
Gate Leakage ◽  
Force Microscopy ◽  
Atomic Force ◽  
Transmission Electron ◽  
Voltage Stress ◽  
Leakage Site

Abstract This article describes the electrical and physical analysis of gate leakage in nanometer transistors using conducting atomic force microscopy (C-AFM), nano-probing, transmission electron microscopy (TEM), and chemical decoration on simulated overstressed devices. A failure analysis case study involving a soft single bit failure is detailed. Following the nano-probing analysis, TEM cross sectioning of this failing device was performed. A voltage bias was applied to exaggerate the gate leakage site. Following this deliberate voltage overstress, a solution of boiling 10%wt KOH was used to etch decorate the gate leakage site followed by SEM inspection. Different transistor leakage behaviors can be identified with nano-probing measurements and then compared with simulation data for increased confidence in the failure analysis result. Nano-probing can be used to apply voltage stress on a transistor or a leakage path to worsen the weak point and then observe the leakage site easier.

Application of Scan Based FA and Advanced Passive Voltage Contrast Technique in Defect Isolation

2003 ◽  
Author(s):  
Michael B. Schmidt ◽  
Noor Jehan Saujauddin
Keyword(s):  
Failure Analysis ◽  
Large Scale ◽  
Fault Isolation ◽  
Electronic Information ◽  
Scan Testing ◽  
Challenging Environment ◽  
Contrast Technique ◽  
Defect Isolation ◽  
Voltage Contrast ◽  
Higher Sensitivity

Abstract Scan testing and passive voltage contrast (PVC) techniques have been widely used as failure analysis fault isolation tools. Scan diagnosis can narrow a failure to a given net and passive voltage contrast can give real-time, large-scale electronic information about a sample at various stages of deprocessing. In the highly competitive and challenging environment of today, failure analysis cycle time is very important. By combining scan FA with a much higher sensitivity passive voltage contrast technique, one can quickly find defects that have traditionally posed a great challenge.

Thin-Die Flip Chip Physical-FA Process Flow

2002 ◽  
Author(s):  
Andrew J. Komrowski ◽  
N. S. Somcio ◽  
Daniel J. D. Sullivan ◽  
Charles R. Silvis ◽  
Luis Curiel ◽  
...  
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
Flip Chip ◽  
Semiconductor Industry ◽  
Organic Substrate ◽  
Fault Isolation ◽  
Preparation Methods ◽  
Chip Technology ◽  
Isolation Test ◽  
Sample Preparation Methods

Abstract The use of flip chip technology inside component packaging, so called flip chip in package (FCIP), is an increasingly common package type in the semiconductor industry because of high pin-counts, performance and reliability. Sample preparation methods and flows which enable physical failure analysis (PFA) of FCIP are thus in demand to characterize defects in die with these package types. As interconnect metallization schemes become more dense and complex, access to the backside silicon of a functional device also becomes important for fault isolation test purposes. To address these requirements, a detailed PFA flow is described which chronicles the sample preparation methods necessary to isolate a physical defect in the die of an organic-substrate FCIP.

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