Fan-Out Wafer-Level Packaging (FOWLP) of Large Chip with Multiple Redistribution Layers (RDLs)

2017 ◽  
Vol 14 (4) ◽  
pp. 123-131 ◽  
Author(s):  
John Lau ◽  
Ming Li ◽  
Nelson Fan ◽  
Eric Kuah ◽  
Zhang Li ◽  
...  
Keyword(s):  
Thin Layer ◽  
Glass Wafer ◽  
Front Side ◽  
Wafer Level ◽  
Molding Compound ◽  
The Third ◽  
Wafer Level Packaging ◽  
Die Attach ◽  
Solder Balls ◽  
Test Package

This study is for fan-out wafer-level packaging with chip-first (die face-up) formation. Chips with Cu contact-pads on the front side and a die attach film on the backside are picked and placed face-up on a temporary-glass-wafer carrier with a thin layer of light-to-heat conversion material. It is followed by compression molding with an epoxy molding compound (EMC) and a post-mold cure on the reconstituted wafer carrier and then backgrinding the molded EMC to expose the Cu contact-pads of the chips. The next step is to build up the redistribution layers (RDLs) from the Cu contact-pads and then mount the solder balls. This is followed by the debonding of the carrier with a laser and then the dicing of the whole reconstituted wafer into individual packages. A 300-mm reconstituted wafer with a package/die ratio = 1.8 and a die-top EMC cap = 100 μm has also been fabricated (a total of 325 test packages on the reconstituted wafer). This test package has three RDLs; the line width/spacing of the first RDL is 5 μm/5 μm, of the second RDL is 10 μm/10 μm, and of the third RDL is 15 μm/15 μm. The dielectric layer of the RDLs is fabricated with a photosensitive polyimide and the conductor layer of the RDLs is fabricated by electrochemical Cu deposition (ECD).

Fan-Out Wafer-Level Packaging (FOWLP) of Large Chip with Multiple Redistribution-Layers (RDLs)

2017 ◽  
Vol 2017 (1) ◽  
pp. 000576-000583 ◽  
Author(s):  
John Lau ◽  
Ming Li ◽  
Nelson Fan ◽  
Eric Kuah ◽  
Zhang Li ◽  
...  
Keyword(s):  
Thin Layer ◽  
Glass Wafer ◽  
Front Side ◽  
Wafer Level ◽  
Molding Compound ◽  
The Third ◽  
Wafer Level Packaging ◽  
Die Attach ◽  
Solder Balls ◽  
Test Package

Abstract This study is for fan-out wafer-level packaging (FOWLP) with chip-first (die face-up) formation. The chips with Cu contact-pads on the front-side and a die attach film (DAF) on the backside are picked and placed face-up on a temporary glass wafer carrier with a thin layer of light-to-heat conversion (LTHC) material. It is followed by compression molding with epoxy molding compound (EMC) and post mold cure (PMC) on the reconstituted wafer carrier, and then backgrinding the molded EMC to expose the Cu contact-pads of the chips. The next step is to build up the redistribution layers (RDLs) from the Cu contact-pads and then mount the solder balls. Next comes the de-bonding of the carrier with a laser, and then the dicing of the whole reconstituted wafer into individual packages. A 300mm reconstituted wafer with a package/die ratio = 1.8 and a die-top EMC cap = 100μm has also been fabricated (a total of 325 test packages on the reconstituted wafer.) This test package has three RDLs; the line width/spacing of the first RDL is 5μm/5μm, of the second RDL is 10μm/10μm, and of the third RDL is 15μm/15μm. The dielectric layer of the RDLs is fabricated with a photosensitive polyimide (PI) and the conductor layer of the RDLs is fabricated by electrochemical Cu deposition (ECD).

Characterizations of Fan-out Wafer-Level Packaging

2017 ◽  
Vol 2017 (1) ◽  
pp. 000557-000562 ◽  
Author(s):  
Ming Li ◽  
Qingqian Li ◽  
John Lau ◽  
Nelson Fan ◽  
Eric Kuah ◽  
...  
Keyword(s):  
Good Control ◽  
High Yield ◽  
Glass Wafer ◽  
Wafer Level ◽  
Process Step ◽  
Wafer Level Packaging ◽  
Die Attach ◽  
Fabrication Defects ◽  
Electroplating Process ◽  
Test Chips

Abstract The calling for smaller form factor, higher I/O density, higher performance and lower cost has made fan-out wafer level packaging (FOWLP) technology the trend. Good control of die position accuracy and molded wafer warpage are some of the keys to achieve high-yield production for FOWLP. In this study, 10mm×10mm test chips were fabricated and attached (chip-first and die face-up) onto 12 inch glass wafer carriers using die-attach-film (DAF). These reconfigured wafers were compression-molded with selected epoxy molding compounds (EMC). Cu bumps (contact-pads) were revealed by grinding, and redistribution layers (RDLs) were fabricated by lithography and electroplating process. The fan-out wafers were evaluated and characterized after each process step with main focus on the die-misplacement/die shift, re-configured wafer warpage, compression molding defects and RDL fabrication defects. The root causes of these defects were investigated and analyzed, while the possible solutions to overcome the defects were proposed and discussed.

Characterization of a Semiconductor Packaging System utilizing Through Glass Via (TGV) Technology

2015 ◽  
Vol 2015 (DPC) ◽  
pp. 001378-001407
Author(s):  
Tim Mobley ◽  
Roupen Keusseyan ◽  
Tim LeClair ◽  
Konstantin Yamnitskiy ◽  
Regi Nocon
Keyword(s):  
Low Cost ◽  
Glass Wafer ◽  
Wafer Level ◽  
Packaging System ◽  
Thin Glass ◽  
Wafer Level Packaging ◽  
Recent Developments ◽  
And Performance ◽  
New Generation ◽  
Semiconductor Packaging

Recent developments in hole formations in glass, metalizations in the holes, and glass to glass sealing are enabling a new generation of designs to achieve higher performance while leveraging a wafer level packaging approach for low cost packaging solutions. The need for optical transparency, smoother surfaces, hermetic vias, and a reliable platform for multiple semiconductors is growing in the areas of MEMS, Biometric Sensors, Medical, Life Sciences, and Micro Display packaging. This paper will discuss the types of glass suitable for packaging needs, hole creation methods and key specifications required for through glass vias (TGV's). Creating redistribution layers (RDL) or circuit layers on both sides of large thin glass wafer poses several challenges, which this paper will discuss, as well as, performance and reliability of the circuit layers on TGV wafers or substrates. Additionally, there are glass-to-glass welding techniques that can be utilized in conjunction with TGV wafers with RDL, which provide ambient glass-to-glass attachments of lids and standoffs, which do not outgas during thermal cycle and allow the semiconductor devices to be attached first without having to reflow at lower temperatures. Fabrication challenges, reliability testing results, and performance of this semiconductor packaging system will be discussed in this paper.

Warpage Characterization of Molded Wafer for Fan-Out Wafer-Level Packaging

2019 ◽  
Vol 142 (1) ◽  
Author(s):  
Hsien-Chie Cheng ◽  
Yan-Cheng Liu
Keyword(s):  
Measurement Data ◽  
Mechanical Analysis ◽  
Volumetric Shrinkage ◽  
Heat Of Reaction ◽  
Wafer Level ◽  
Molding Process ◽  
Scanning Calorimetry ◽  
Molding Compound ◽  
Wafer Level Packaging

Abstract This study presents a comprehensive assessment of the process-induced warpage of molded wafer for chip-first, face-down fan-out wafer-level packaging (FOWLP) during the fan-out fabrication process. A process-dependent simulation methodology is introduced, which integrates nonlinear finite element (FE) analysis and element death-birth technique. The effects of the cure-dependent volumetric shrinkage, geometric nonlinearity, and gravity loading on the process-induced warpage are examined. The study starts from experimental characterization of the temperature-dependent material properties of the applied liquid type epoxy molding compound (EMC) system through dynamic mechanical analysis (DMA) and thermal mechanical analysis. Furthermore, its cure state (heat of reaction and degree of cure (DOC)) during the compression molding process (CMP) is measured by differential scanning calorimetry (DSC) tests. Besides, the cure dependent-volumetric (chemical) shrinkages of the EMC system after the in-mold cure (IMC) and postmold cure (PMC) are experimentally determined by which the volumetric shrinkage at the gelation point is predicted through a linear extrapolation approach. To demonstrate the effectiveness of the proposed theoretical model, the prediction results are compared against the inline warpage measurement data. One possible cause of the asymmetric/nonaxisymmetric warpage is also addressed. Finally, the influences of some geometric dimensions on the warpage of the molded wafer are identified through parametric analysis.

SiP(System in Package) Solutions with Wafer Level Packaging Technology

2011 ◽  
Vol 2011 (DPC) ◽  
pp. 002226-002253 ◽  
Author(s):  
In Soo Kang ◽  
Jong Heon (Jay) Kim
Keyword(s):  
Embedded System ◽  
High Performance ◽  
Low Cost ◽  
Wafer Level ◽  
Molding Compound ◽  
Wafer Level Packaging ◽  
Ic Packaging ◽  
Chip Size ◽  
Bonding Technology ◽  
Small Form Factor

In mobile application, the WLP technology has been developing to make whole package size almost same as chip size. However, the I/O per chip unit area has increased so that it gets difficult to realize ideal pad pitch for better reliability. Recently, to achieve the thin and small size, high performance and low cost semiconductor package, Embedding Die and Fanout Technologies have been suggested and developed based on wafer level processing. In this work, as a solution of system in package, wafer level embedded package and fanout technology will be reviewed. Firstly, Wafer level embedded System in Package (WL-eSiP) which has daughter chip (small chip) embedded inside mother chip (bigger chip) without any special substrate has been suggested and developed. To realize wafer level embedded system in package (WL-eSiP), wafer level based new processes like wafer level molding for underfilling and encapsulation by molding compound without any special substrate have been applied and developed, including high aspect ratio Cu bumping, mold thinning and chip-to-wafer flipchip bonding. Secondly, Fan-out Package is considered as alternative package structure which means merged package structure of WLCSP (wafer level chip size package) and PCB process. We can make IC packaging widen area for SIP(System in Package) or 3D package. In addition, TSV and IPD are key enabling technology to meet market demands because TSV interconnection can provide wider bandwidth and high transmission speed due to vertical one compared to wire bonding technology and IPD can provide higher performance, more area saving to be assembled and small form factor compared to discrete passive components.

Optimization of laser release layer, glass carrier, and organic build-up layer to enable RDL-first fan-out wafer-level packaging

2016 ◽  
Vol 2016 (1) ◽  
pp. 000190-000195 ◽  
Author(s):  
Alvin Lee ◽  
Jay Su ◽  
Baron Huang ◽  
Ram Trichur ◽  
Dongshun Bai ◽  
...  
Keyword(s):  
High Speed ◽  
Process Integration ◽  
Cost Effective ◽  
Wafer Level ◽  
Molding Compound ◽  
Fine Line ◽  
Glass Substrates ◽  
Laser Ablation Process ◽  
Wafer Level Packaging ◽  
Increasing Demand

Abstract With increasing demand for mobile devices to be lighter and thinner and consume less power while operating at high speed and high bandwidth, many equipment suppliers and assembly participants have invested great efforts to achieve fine-line fan-out wafer-level packaging (FOWLP). However, the inherent warp of reconstituted wafers, which can contribute to poor die placement accuracy and/or delamination at the interface of the build-up layer and carrier, remains a major challenge. In this study, the interactions among laser release layer, glass carrier, and build-up layer were evaluated for optimization of redistribution layer (RDL)–first FOWLP as a foundation to move toward fine-line FOWLP. In this study, a series of experiments incorporating glass carrier, laser release layer, and build-up layers were carried out to determine the optimal setup for RDL-first FOWLP. First, glass carriers (300 mm × 300 mm × 0.7 mm) with coefficients of thermal expansion of 3 and 8 ppm/°C were treated with 150-nm laser release layers. After deposition of 0.1 μm of sacrificial material on the glass carrier, 8-μm build-up layers were coated and patterned by lithography to electroplate Cu interconnections with a density of approximately 10% of the surface area. Subsequent to die attachment, molding compound was applied on top to form a 200-μm protective overcoat. The reconstituted wafer was then separated from the glass carrier through a laser ablation process using a 308-nm laser to complete the design of experiments (DOE). An experiment to study the correlation of glass carrier, laser release layer, build-up layers, and molding compound in RDL-first FOWLP processes is discussed to address full process integration on 300-mm glass substrates. The combination of glass carrier, laser release layer, build-up layer, and molding compound will pave the way for realizing cost-effective RDL-first FOWLP on panel-size substrates.

Wafer Level Packaging of RF MEMS for Flip Chip Assembly

2003 ◽  
Author(s):  
J. Wei ◽  
B. K. Lok ◽  
P. C. Lim ◽  
M. L. Nai ◽  
H. J. Lu ◽  
...  
Keyword(s):  
Flip Chip ◽  
Rf Mems ◽  
Bonding Temperature ◽  
Etching Process ◽  
Glass Wafer ◽  
Wafer Level ◽  
Pressure Balance ◽  
Etching Depth ◽  
Wafer Level Packaging ◽  
Via Holes

In this paper, the development of wafer level packaging of radio frequency (RF) microelectromechanical system (MEMS) is reported. The packaging process consists of wafer bonding, wafer thinning, via etching, plating, under-bump-metallization (UBM) and bumping processes. 6-inch Si and glass wafers are used in the study. RF MEMS devices are fabricated on Si wafers and sandwiched between Si and glass cap wafers. To maintain the pressure balance between the cavities and outside world after bonding process, Si and glass wafers are anodically bonded at a pressure of 2 bar and a bonding temperature of 400 °C. The cavities are hermetically sealed. The glass wafer of the bonded pair is thinned down to 100 μm using mechanical polishing and chemical etching, the good uniformity of the wafer thickness is maintained with etching process. A layer of Cr/Au is sputtered and patterned as the hard mask for glass via etching process. Via holes with undercut closer to the etching depth are formed in HF+HNO3 acid. After stripping the metal mask, a seed layer of TiW/Cu is deposited using sputtering and plating processes. TiW layer is used to enhance the adhesion of metal and glass. With the completion of the re-routing and via metallization processes, benzocyclobutene (BCB) photoresist is used to planarize via holes and opened for UBM process. Finally, the packaged devices can be assembled using flip chip approach.

scholarly journals Improved Die Attribute Recognition via Colored Glass Wafer

2021 ◽  
pp. 104-108
Author(s):  
Alyssa Grace Gablan ◽  
Jerome Dinglasan ◽  
Frederick Ray Gomez
Keyword(s):  
Pattern Recognition ◽  
Recognition System ◽  
Industrial Applications ◽  
Process Equipment ◽  
Colored Glass ◽  
Glass Wafer ◽  
Wafer Level ◽  
Design Standards ◽  
Die Attach ◽  
Cutting Sequence

The rise of various Wafer technologies has been developed based on industries and applications requirement. Highest quality of material characterization is complex and requires specialized process equipment and manufacturing procedures to meet defined design standards. The paper presents distinctive glass wafer-level fabrication technology that will enhance its properties with respect to pattern recognition system (PRS) at back-end manufacturing for industrial applications. Feasibility of colored glass wafer has been built into proposed conception to manufacture wafer-level packaging. The idea from transparent to colored glass wafer came from manufacturing key challenges that cutting sequence during pattern recognition cannot be distinguished. The proposed solution will mitigate high risk of misaligned cut at wafer sawing and its potential attachment on leadframe during die attach. glass wafer dice, transparent in nature, intermittently encountered multiple PRS assist during Wafer sawing and die attach as it hardly recognizes its cutting positions. Since dependent of machine capability limitations, misaligned cut is inevitable and usually happen occasionally. Addressing its unrecognizable characteristic, proposed colored glass wafer and with visible outline and saw lane fabrication was conceptualized instead of seeking ideal and high equipment model that can differentiate its opaque feature. The colored glass wafer and with visible outline and saw lane naturally creates segmentation visibly and will not be parameter dependent during manufacturing.

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