Advanced Substrate Applied Fluxing Underfill for Bonding of Fine Pitch Solder Capped Cu Pillars to Oxidized Cu Substrates

2012 ◽  
Vol 2012 (DPC) ◽  
pp. 000924-000943
Author(s):  
Russell Stapleton ◽  
Jim Greig
Keyword(s):  
Cross Sections ◽  
Flip Chip ◽  
Low Cost ◽  
Cost Effective ◽  
Filler Loading ◽  
Thermal Compression ◽  
Transparent Substrate ◽  
Fine Pitch ◽  
Before And After ◽  
Cu Substrates

Underfill solutions for fine pitch flip chip assemblies is an active area of development. Non-conductive films (NCF) and pastes (NCP) have shown great potential in bridging the gap between no-flow and capillary underfills for improving the reliability of fine pitched devices. But NCFs and NCPs require costly passivated pad finishes (e.g. Au, Sn, Ni, OSP) or careful substrate handling for proper solder joint formation. In this paper, we will describe a new class of underfill material that benefits from the growing trend of using thermal compression bonding as a cost effective alternative to mass reflow based underfilling processes (e.g. capillary and no-flow). This material is a fluxing NCP that is useful for a wide variety of fine pitch substrates, including low cost Cu. The material we will demonstrate contains many advanced features: high filler loading, strong flux activity, long work life, off-tool pre-dispense, low stress, high Tg, high modulus and rapid cure. The all-in-one underfill demonstrated in this paper is applied by using a screen printing process, where the material is applied to all of the chip sites in one step achieving excellent application efficiency and wetting/conformity to the substrate. The substrate is glass, containing a 4x4 array of die sites. Each of the die sites are 5x5mm in size with a full area array of 2501 Cu pads (50um pads on 100um pitch) that are pre-oxidized for 1h at 175C in air prior to printing (to simulate a dehydration bake). This transparent substrate was chosen to show the robust nature of the underfill for fluxing, stability and void-free placement/cure. Images of the substrate, before and after chip bonding will be given, along with cross sections. Details of the material properties will also be discussed.

Wafer Level Assembly Technique Development for Fine Pitch Flip Chip 3D Die-to-Wafer Integration

2010 ◽  
Vol 2010 (1) ◽  
pp. 000548-000553
Author(s):  
Zhaozhi Li ◽  
Brian J. Lewis ◽  
Paul N. Houston ◽  
Daniel F. Baldwin ◽  
Eugene A. Stout ◽  
...  
Keyword(s):  
Flip Chip ◽  
Low Cost ◽  
Three Dimensional ◽  
Cost Effective ◽  
Market Demand ◽  
Wafer Level ◽  
Packaging Technology ◽  
Fine Pitch ◽  
3D Packaging ◽  
Assembly Technique

Three Dimensional (3D) Packaging has become an industry obsession as the market demand continues to grow toward higher packaging densities and smaller form factor. In the meanwhile, the 3D die-to-wafer (D2W) packaging structure is gaining popularity due to its high manufacturing throughput and low cost per package. In this paper, the development of the assembly process for a 3D die-to-wafer packaging technology, that leverages the wafer level assembly technique and flip chip process, is introduced. Research efforts were focused on the high-density flip chip wafer level assembly techniques, as well as the challenges, innovations and solutions associated with this type of 3D packaging technology. Processing challenges and innovations addressed include flip chip fluxing methods for very fine-pitch and small bump sizes; wafer level flip chip assembly program creation and yield improvements; and set up of the Pb-free reflow profile for the assembled wafer. 100% yield was achieved on the test vehicle wafer that has totally 1,876 flip chip dies assembled on it. This work has demonstrated that the flip chip 3D die-to-wafer packaging architecture can be processed with robust yield and high manufacturing throughput, and thus to be a cost effective, rapid time to market alternative to emerging 3D wafer level integration methodologies.

Nonlinear-Time-Dependent Analysis of Micro Via-In-Pad Substrates for Solder Bumped Flip Chip Applications

2002 ◽  
Vol 124 (3) ◽  
pp. 205-211 ◽  
Author(s):  
John H. Lau ◽  
S. W. Ricky Lee ◽  
Stephen H. Pan ◽  
Chris Chang
Keyword(s):  
Cross Sections ◽  
Flip Chip ◽  
Printed Circuit Board ◽  
Low Cost ◽  
Circuit Board ◽  
Test Results ◽  
Pcb Assembly ◽  
Creep Analysis ◽  
Chip Scale Package ◽  
Time Dependent Analysis

An elasto-plastic-creep analysis of a low-cost micro via-in-pad (VIP) substrate for supporting a solder bumped flip chip in a chip scale package (CSP) format which is soldered onto a printed circuit board (PCB) is presented in this study. Emphasis is placed on the design, materials, and reliability of the micro VIP substrate and of the micro VIP CSP solder joints on PCB. The solder is assumed to obey Norton’s creep law. Cross-sections of samples are examined for a better understanding of the solder bump, CSP substrate redistribution, micro VIP, and solder joint. Also, the thermal cycling test results of the micro VIP CSP PCB assembly is presented.

Thermally Activated Bumping Process using Sn3.0Ag0.5Cu Solder Powder for Low-Cost Interposers

2013 ◽  
Vol 2013 (1) ◽  
pp. 000420-000423
Author(s):  
Kwang-Seong Choi ◽  
Ho-Eun Bae ◽  
Haksun Lee ◽  
Hyun-Cheol Bae ◽  
Yong-Sung Eom
Keyword(s):  
Screen Printing ◽  
Flip Chip ◽  
Solder Bump ◽  
Low Cost ◽  
Organic Substrate ◽  
Lead Free ◽  
Lead Free Solder ◽  
Thermally Activated ◽  
Fine Pitch ◽  
Free Solder

A novel bumping process using solder bump maker (SBM) is developed for fine-pitch flip chip bonding. It features maskless screen printing process with the result that a fine-pitch, low-cost, and lead-free solder-on-pad (SoP) technology can be easily implemented. The process includes two main steps: one is the thermally activated aggregation of solder powder on the metal pads on a substrate and the other is the reflow of the deposited powder on the pads. Only a small quantity of solder powder adjacent to the pads can join the first step, so a quite uniform SoP array on the substrate can be easily obtained regardless of the pad configurations. Through this process, an SoP array on an organic substrate with a pitch of 130 μm is, successfully, formed.

Before-and-After Empirical Bayes Evaluation of Citywide Installation of Driver Feedback Signs

2020 ◽  
Vol 2674 (4) ◽  
pp. 419-427
Author(s):  
Mingjian Wu ◽  
Karim El-Basyouny ◽  
Tae J. Kwon
Keyword(s):  
Traffic Safety ◽  
Spatial Data ◽  
Empirical Bayes ◽  
Large Scale ◽  
Low Cost ◽  
Cost Effective ◽  
Before And After ◽  
Feedback Sign ◽  
Driver Feedback ◽  
Road Segments

Speeding is a leading factor that contributes to approximately one-third of all fatal collisions. Over the past decades, various passive/active countermeasures have been adopted to improve drivers’ compliance to posted speed limits to improve traffic safety. The driver feedback sign (DFS) is considered a low-cost innovative intervention that is being widely used, in growing numbers, in urban cities to provide positive guidance for motorists. Despite their documented effectiveness in reducing speeds, limited literature exists on their impact on reducing collisions. This study addresses this gap by designing a before-and-after study using the empirical Bayes method for a large sample of urban road segments. Safety performance functions and yearly calibration factors are developed to quantify the sole effectiveness of DFS using large-scale spatial data and a set of reference road segments within the city of Edmonton, Alberta, Canada. Likewise, the study followed a detailed economic analysis based on three collision-costing criteria to investigate if DFS was indeed a cost-effective intervention. The results showed significant collision reductions that ranged from 32.5% to 44.9%, with the highest reductions observed for severe speed-related collisions. The results further attested that the benefit–cost ratios, combining severe and property-damage-only collisions, ranged from 8.2 to 20.2 indicating that DFS can be an extremely economical countermeasure. The findings from this study can provide transportation agencies in need of implementing cost-efficient countermeasures with a tool they need to design a long-term strategic deployment plan to ensure the safety of traveling public.

Ultra-fine pitch Package on Package solution for high bandwidth mobile applications

2013 ◽  
Vol 2013 (DPC) ◽  
pp. 001870-001893
Author(s):  
Rajesh Katkar ◽  
Zhijun Zhao ◽  
Ron Zhang ◽  
Rey Co ◽  
Laura Mirkarimi
Keyword(s):  
Flip Chip ◽  
Cost Effective ◽  
Temperature Cycling ◽  
Memory Bandwidth ◽  
Free Standing ◽  
Element Analysis ◽  
Fine Pitch ◽  
Solder Balls ◽  
High Bandwidth ◽  
Reliability Performance

Existing Package-on-Package (PoP) solutions are rapidly approaching the logic memory bandwidth capacity in the multi-core mobile processor packages. Package on Package stack using the conventional solder balls has a serious pitch limitation below 400um. The through mold via interconnects may reduce the pitch to 300um; however, this technology is believed to reach a limitation below 300 um. Other approaches including the use of PCB interposers between the Logic and the memory face similar challenges; however, they are cumbersome in the assembly process and expensive. Although Through Silicon Via stacking is expected to achieve the ultimate high bandwidth required to support multi-core mobile processors, the technology must overcome the challenges in process, infrastructure, supply chain and cost. Bond Via Array (BVA) technology addresses all of these issues while enabling high bandwidth PoP stacking of more than 1000 high aspect ratio interconnects at less than 200um within the standard package footprint. BVA is a cost effective, ultra-fine pitch, high density PoP stacking solution that will assist in driving high logic-memory bandwidth applications with standard assembly equipment and processes. This is achieved by encapsulating the logic package after forming free-standing wire bonds along the periphery of its flip chip substrate. The wire protrusions formed above the mold cap at the top of the package are then connected to the BGA at the bottom of the memory package during a standard reflow operation. In this work, the initial evaluation test vehicle with 432 PoP interconnects at 240um pitch within a standard 14 x 14mm package foot print is demonstrated. The important technological challenges we overcame to fabricate the first prototypes will be discussed. The reliability performance describing the temperature cycling, high temperature storage, autoclave and drop testing will be discussed. Finite element analysis modeling used to optimize the package structure will be presented.

Reliability of Passive UHF RFID Copper Tags on Plywood Substrate in High Humidity Conditions

2016 ◽  
Vol 2016 (NOR) ◽  
pp. 12-16 ◽  
Author(s):  
Erja Sipilä ◽  
Johanna Virkki ◽  
Lauri Sydänheimo ◽  
Leena Ukkonen
Keyword(s):  
Moisture Absorption ◽  
Low Cost ◽  
Cost Effective ◽  
High Volume ◽  
High Humidity ◽  
Uhf Rfid ◽  
Passive Uhf Rfid ◽  
Before And After ◽  
Moist Environment ◽  
Read Range

The growth of the wireless world, especially the increasing popularity of the Internet of Things, has created a need for cost-effective and environmentally friendly electronics. Great potential lies especially in versatile applications of passive UHF RFID components. However, the reliability of these components is a major issue to be addressed. This paper presents a preliminary reliability study of glue-coated and non-coated brush-painted copper tags on a plywood substrate in high humidity conditions. The passive UHF RFID components presented in this paper are fabricated using brush-painting and photonic sintering of cost-effective copper oxide ink directly on a plywood substrate. The performance of the glue-coated and non-coated tags is evaluated through wireless tag measurements before and after high humidity testing. The measurement results show that the copper tags on plywood substrate initially achieve peak read ranges of 7–8 meters and the applied coating does not affect to the read range. Moisture does not prevent the coated tags from working in a tolerable way, although the tag performance slightly temporarily decreases due to the moisture absorption. However, when the moisture exposure is long, the performance degradation comes irreversible. The absorbed moisture decreases the read range of the non-coated tags and the performance does not return back to normal after drying. Hence, the coating improves the reliability of the tags in a moist environment compared to the non-coated tags. Based on our results, the plywood material and the used manufacturing methods are very potential for low-cost, high-volume green electronics manufacturing.

Thin Film Packaging Reinforcement for Overmolded MEMS

2010 ◽  
Vol 2010 (DPC) ◽  
pp. 001095-001119
Author(s):  
Gillot Charlotte ◽  
Jean-Louis Pornin ◽  
Christophe Billard ◽  
Emannuelle Lagoute ◽  
Mihel Pellat ◽  
...  
Keyword(s):  
Thin Film ◽  
Flip Chip ◽  
Low Cost ◽  
Short Circuit ◽  
Cost Effective ◽  
Wafer Level ◽  
Silicon Area ◽  
Mechanical Constraints ◽  
Test Card ◽  
Manufacturing Technologies

Thin Film packaging (TFP) is now well known at CEA/LETI and mainly used as a protection for MEMS against degradation which can occur during back end processes: TFP is strong enough to endure the mechanical constraints due to grinding, handling and protects the device from water during the sawing step. Our TFP process is also compatible with under bump metallisation, balling and flip chip processes. The main advantages of our TFP is a very low lost of silicon area, a low cost process with 3 mask levels, and is performed on equipments commonly used in IC fab. In this paper we will speek about process improvement for a TFP overmolded. The thermo-mechanical constraints due to the standard overmolding step (100 bars and 200°C) are much more challenging for TFP: the cavity is about 5 μm high, the cap layer 2μm thick and the polymer plugging layer 6μm thick. So TFP needs to be reinforced to withstand these high constraints. Two processes using conventional IC manufacturing technologies have been developed at wafer level with two materials. 200μm and 500μm wide cavities with TFP were reinforced with these processes and first tested under pneumatically pressure at room temperature: in case of contact between the cap and the substrate, a short circuit is measured between one electrode on the substrate and another electrode behind the cap. Then, the same devices were overmolded at 75 bars and 100 bars at 185°C. In the same run, BAW resonators with TFP and one type of reinforcement were overmolded at 100 bars. The electrical performances of these resonators after overmolding fit very well to the modelling of the test card and are very good. This Compatibility between TFP and overmolding constraints could be a cost effective solution in MEMS packaging.

Fine pitch low-cost bumping for flip chip technology

2003 ◽  
Author(s):  
Szu-Wei Lu ◽  
Ruoh-Huey Uang ◽  
Kuo-Chuan Chen ◽  
Hsu-Tien Hu ◽  
Ling-Chen Kung ◽  
...  
Keyword(s):  
Flip Chip ◽  
Low Cost ◽  
Chip Technology ◽  
Fine Pitch
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